ATmega16 datasheet(158/357 Pages) ATMEL

158 / 357 page

158

2466S–AVR–05/09

ATmega16(L)

figure), to decide if a valid start bit is received. If two or more of these three samples have logical

high levels (the majority wins), the start bit is rejected as a noise spike and the receiver starts

looking for the next high to low-transition. If however, a valid start bit is detected, the clock recov-

ery logic is synchronized and the data recovery can begin. The synchronization process is

repeated for each start bit.

Asynchronous Data

Recovery

When the receiver clock is synchronized to the start bit, the data recovery can begin. The data

recovery unit uses a state machine that has 16 states for each bit in normal mode and 8 states

for each bit in Double Speed mode. Figure 74 shows the sampling of the data bits and the parity

bit. Each of the samples is given a number that is equal to the state of the recovery unit.

Figure 74. Sampling of Data and Parity Bit

The decision of the logic level of the received bit is taken by doing a majority voting of the logic

value to the three samples in the center of the received bit. The center samples are emphasized

on the figure by having the sample number inside boxes. The majority voting process is done as

follows: If two or all three samples have high levels, the received bit is registered to be a logic 1.

If two or all three samples have low levels, the received bit is registered to be a logic 0. This

majority voting process acts as a low pass filter for the incoming signal on the RxD pin. The

recovery process is then repeated until a complete frame is received. Including the first stop bit.

Note that the receiver only uses the first stop bit of a frame.

Figure 75 shows the sampling of the stop bit and the earliest possible beginning of the start bit of

the next frame.

Figure 75. Stop Bit Sampling and Next Start Bit Sampling

The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop

bit is registered to have a logic 0 value, the Frame Error (FE) Flag will be set.

A new high to low transition indicating the start bit of a new frame can come right after the last of

the bits used for majority voting. For Normal Speed mode, the first low level sample can be at

point marked (A) in Figure 75. For Double Speed mode the first low level must be delayed to (B).

the receiver.

BIT n

123

678

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

0/1

STOP 1

123

0/1

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

(A)

(B)

(C)

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