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TLE8262E датащи(PDF) 75 Page - Infineon Technologies AG |
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TLE8262E датащи(HTML) 75 Page - Infineon Technologies AG |
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75 / 93 page ![]() Data Sheet 75 Rev. 1.0, 2009-03-31 TLE8262E Serial Peripheral Interface 15.5.2.2 Interrupt Register Encoder Table 16 lists all interrupts the SBC can generates. The microcontroller should read the correct register to release the INT pin. By default, all interrupt sources are enabled. The microcontroller can decide to inhibit a specific interrupt source. Table 16 Interrupt Register encoder 1) CS Bit Name Default Value (INPUT) Default Value (OUT) Data Input Data Output Configuration select 000 (Wake register interrupt) 000 WK CAN 1 0 Interrupt enabled (1) disabled (0) for wake event on CAN Wake on CAN (1) WKLINx 1 0 Interrupt enabled (1) disabled (0) for wake event on LIN Wake on LINx (1) WK 1 WK pin WK 0 WK pin 11 00 Interrupt enabled (1) disabled (0) for wake pin event. 00 No interrupt 10 Interrupt for a LOW to HIGH transition on WK 01 Interrupt for HIGH to LOW transition on WK 11 Interrupt for both HIGH to LOW and LOW to HIGH on WK Wake on WK pin 00 No wake 10 Interrupt for a LOW to HIGH transition on WK 01 Interrupt for HIGH to LOW transition on WK 11 Interrupt for both HIGH to LOW and LOW to HIGH on WK Cyclic WK n.a 0 n.a Cyclic WK (1) INT n.a 0 n.a Indicates that there is a status bit or uncleared event in configuration select 001 and/or 010. If set read the two register |
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