PCF8576DTSLASHS400SLASH2 datasheet(23/52 Pages) NXP

23 / 52 page

PCF8576D_9

Product data sheet

Rev. 09 — 25 August 2009

23 of 52

NXP Semiconductors

PCF8576D

Universal LCD driver for low multiplex rates

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I2C-bus is shown in Figure 16.

7.16.5 I2C-bus controller

The PCF8576D acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or

transmit data to an I2C-bus master receiver. The only data output from the PCF8576D are

the acknowledge signals of the selected devices. Device selection depends on the

I2C-bus slave address, on the transferred command data and on the hardware

subaddress.

In single device applications, the hardware subaddress inputs A0, A1 and A2 are normally

tied to VSS which deﬁnes the hardware subaddress 0. In multiple device

applications A0, A1 and A2 are tied to VSS or VDD in accordance with a binary coding

scheme such that no two devices with a common I2C-bus slave address have the same

hardware subaddress.

7.16.6 Input ﬁlters

To enhance noise immunity in electrically adverse environments, RC low-pass ﬁlters are

provided on the SDA and SCL lines.

7.16.7 I2C-bus protocol

Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8576D.

The least signiﬁcant bit of the slave address that a PCF8576D will respond to is deﬁned by

the level tied to its SA0 input. The PCF8576D is a write-only device and will not respond to

a read access. Having two reserved slave addresses allows the following on the same

I2C-bus:

• Up to 16 PCF8576Ds for very large LCD applications

• The use of two types of LCD multiplex drive.

Fig 16. Acknowledgement of the I2C-bus

mbc602

START

condition

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from

master

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