PCF8576DTSLASH2 datasheet(19/52 Pages) NXP

19 / 52 page

PCF8576D_9

Product data sheet

Rev. 09 — 25 August 2009

19 of 52

NXP Semiconductors

PCF8576D

Universal LCD driver for low multiplex rates

The following applies to Figure 12:

• In the static drive mode, the eight transmitted data bits are placed in row 0 of eight

successive 4-bit RAM words.

• In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into

row 0 and 1 of four successive 4-bit RAM words.

• In the 1:3 multiplex mode, the eight bits are placed in triples into row 0, 1 and 2 to

three successive 4-bit RAM words, with bit 3 of the third address left unchanged. It is

not recommended to use this bit in a display because of the difﬁcult addressing. This

last bit may, if necessary, be controlled by an additional transfer to this address but

care should be taken to avoid overwriting adjacent data because always full bytes are

transmitted.

• In the 1:4 multiplex mode, the eight transmitted data bits are placed in quadruples into

row 0, 1, 2 and 3 of two successive 4-bit RAM words.

7.11 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer.

This allows the loading of an individual display data byte, or a series of display data bytes,

into any location of the display RAM. The sequence commences with the initialization of

the data pointer by the load-data-pointer command (see Section 7.17).

Following this command, an arriving data byte is stored at the display RAM address

indicated by the data pointer. The ﬁlling order is shown in Figure 12.

After each byte is stored, the content of the data pointer is automatically incremented by a

value dependent on the selected LCD drive mode:

After each byte is stored, the contents of the data pointer is automatically incremented by

a value dependent on the selected LCD drive mode:

• In static drive mode by eight

• In 1:2 multiplex drive mode by four

• In 1:3 multiplex drive mode by three

• In 1:4 multiplex drive mode by two

If an I2C-bus data access is terminated early then the state of the data pointer is unknown.

The data pointer should be re-written prior to further RAM accesses.

7.12 Subaddress counter

The storage of display data is determined by the contents of the subaddress counter.

Storage is allowed to take place only when the contents of the subaddress counter match

with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is

deﬁned by the device-select command (see Section 7.17). If the contents of the

subaddress counter and the hardware subaddress do not match then data storage is

inhibited but the data pointer is incremented as if data storage had taken place. The

subaddress counter is also incremented when the data pointer overﬂows.

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