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PCF8576DT/2 датащи(PDF) 17 Page - NXP Semiconductors |
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PCF8576DT/2 датащи(HTML) 17 Page - NXP Semiconductors |
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17 / 52 page ![]() PCF8576D_9 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 — 25 August 2009 17 of 52 NXP Semiconductors PCF8576D Universal LCD driver for low multiplex rates In the 1:2 multiplex drive mode, BP0 and BP2, BP1 and BP3 all carry the same signals and may also be paired to increase the drive capabilities. In the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 7.10 Display RAM The display RAM is a static 40 × 4-bit RAM which stores LCD data. A logic 1 in the RAM bit-map indicates the on-state of the corresponding LCD element; similarly, a logic 0 indicates the off-state. There is a one-to-one correspondence between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane outputs. The display RAM bit map Figure 11 shows the rows 0 to 3 which correspond with the backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first, second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2 and BP3 respectively. When display data is transmitted to the PCF8576D, the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for an acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triplets or quadruplets. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Figure 12; the RAM filling organization depicted applies equally to other LCD types. Display RAM bit map showing direct relationship between RAM addresses and segment outputs; also between bits in a RAM word and the backplane outputs. Fig 11. Display RAM bit map 0 0 1 2 3 1234 35 36 37 38 39 display RAM addresses (columns)/segment outputs (S) display RAM bits (rows)/ backplane outputs (BP) mbe525 |
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