MCP3901 datasheet(30/60 Pages) MICROCHIP

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MCP3901

DS22192A-page 30

5.8

Power-on Reset

The MCP3901 contains an internal POR circuit that

monitors analog supply voltage AVDD during operation.

The typical threshold for a power-up event detection is

4.2V +/-5%. The POR circuit has a built-in hysteresis

for improved transient spikes immunity that has a

typical value of 200 mV. Proper decoupling capacitors

(0.1 µF ceramic and 10 µF tantalum) should be

mounted as close as possible to the AVDD pin,

providing additional transient immunity.

Figure 5-4

illustrates

the

different

conditions

power-up and a power-down event in the typical

conditions. All internal DC biases are not settled until at

least 50 µs after system POR. Any DR pulses during

this time after system reset should be ignored. After

POR, DR pulses are present at the pin with all the

default conditions in the configuration registers.

Both AVDD and DVDD power supplies are independent.

Since AVDD is the only power supply that is monitored,

it is highly recommended to power up DVDD first as a

power-up sequence. If AVDD is powered up first, it is

highly recommended to keep RESET pin low during the

whole power-up sequence.

FIGURE 5-4:

Power-on Reset Operation.

5.9

RESET Effect On Delta Sigma

Modulator/SINC Filter

When the RESET pin is low, both ADCs will be in Reset

and output code 0x0000h. The RESET pin performs a

hard reset (DC biases still on, part ready to convert)

and clears all charges contained in the sigma delta

modulators. The comparators output is 0011 for each

ADC.

The SINC filters are all reset, as well as their double

output buffers. This pin is independent of the serial

interface. It brings the CONFIG registers to the default

state. When RESET is low, any write with the SPI

interface will be disabled and will have no effect. All

output pins (SDO, DR, MDAT0/1) are high impedance,

and no clock is propagated through the chip.

5.10

Phase Delay Block

The MCP3901 incorporates a phase delay generator

which ensures that the two ADCs are converting the

inputs with a fixed delay between them. The two ADCs

are synchronously sampling but the averaging of

modulator outputs is delayed so that the SINC filter

outputs (thus the ADC outputs) show a fixed phase

delay, as determined by the PHASE register setting.

The phase register (PHASE<7:0>) is a 7 bit + sign,

MSB first, two's complement register that indicates how

much phase delay there is to be between Channel 0

and Channel 1. The reference channel for the delay is

Channel 1 (typically the voltage channel for power

metering applications). When PHASE<7:0> is positive,

Channel 0 is lagging versus Channel 1. When

PHASE<7:0> is negative, Channel 0 is leading versus

Channel 1. The amount of delay between two ADC

conversions is given by the following formula:

EQUATION 5-4:

The timing resolution of the phase delay is 1/DMCLK or

1 µs in the default configuration with MCLK = 4 MHz.

The data ready signals are affected by the phase delay

settings. Typically, the time difference between the data

ready pulses of channel 0 and channel 1 is equal to the

phase delay setting.

AVDD

4.2V

DEVICE

MODE

RESET

PROPER

OPERATION

RESET

Time

50 µs

tPOR

Note:

A detailed explanation of the data ready

pin (DR) with phase delay is present in

Section 6.10 “Data Ready Latches And

Data Ready Modes (DRMODE<1:0>)”.

Delay

Phase Register Code

DMCLK

--------------------------------------------------

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