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MCP3302 датащи(PDF) 20 Page - Microchip Technology

номер детали MCP3302
подробное описание детали  13-Bit Differential Input, Low Power A/D Converter with SPI Serial Interface
PDF  46 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

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MCP3302/04
DS21697E-page 20
© 2008 Microchip Technology Inc.
FIGURE 5-3:
Analog Input Model.
5.2.1
MAINTAINING MINIMUM CLOCK
SPEED
When the MCP3302/04 initiates, charge is stored on
the sample capacitor. When the sample period is
complete, the device converts one bit for each clock
that is received. It is important for the user to note that
a slow clock rate will allow charge to bleed off the
sample cap while the conversion is taking place. For
the MCP330X devices, the recommended minimum
clock speed during the conversion cycle (TCONV) is
105 kHz. Failure to meet this criteria may induce
linearity errors into the conversion outside the rated
specifications. It should be noted that during the entire
conversion cycle, the
A/D converter does not have
requirements for clock speed or duty cycle, as long as
all timing specifications are met.
5.3
Biasing Solutions
For pseudo-differential bipolar operation, the biasing
circuit (shown in Figure 5-4) shows a single ended
input AC coupled to the converter. This configuration
will give a digital output range of -4096 to +4095. With
the 2.5V reference, the LSB size equal to 610 µV.
Although the ADC is not production tested with a 2.5V
reference as shown, linearity will not change more than
0.1 LSB. See Figure 2-2 and Figure 2-9 for DNL and
INL errors versus VREF at VDD = 5V. A trade-off exists
between the high-pass corner and the acquisition time.
The value of C will need to be quite large in order to
bring down the high-pass corner. The value of R will
need to be 1 kΩ, or less, since higher input
impedances require additional acquisition time. Using
the RC values in Figure 5-4, we have a 100 Hz corner
frequency. See Figure 2-12 for relation between input
impedance and acquisition time.
FIGURE 5-4:
Pseudo-differential biasing
circuit for bipolar operation.
CPIN
VA
RSS CHx
7pF
VT = 0.6V
VT = 0.6V
ILEAKAGE
Sampling
Switch
SS
RS = 1 kΩ
CSAMPLE
= DAC capacitance
VSS
VDD
= 25 pF
±1 nA
Legend
VA
= signal source
RSS = source impedance
CHx
= input channel pad
CPIN = input pin capacitance
VT = threshold voltage
ILEAKAGE = leakage current at the pin
due to various junctions
SS
= sampling switch
RS = sampling switch resistor
CSAMPLE = sample/hold capacitance
VDD = 5V
0.1 µF
IN+
IN-
VREF
MCP330X
1µF
MCP1525
VIN
VOUT
0.1 µF
1k
Ω
10 µF
VIN
R
C



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