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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AS4LC4M16DG-5S/XT датащи(PDF) 9 Page - Austin Semiconductor |
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AS4LC4M16DG-5S/XT датащи(HTML) 9 Page - Austin Semiconductor |
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9 / 25 page  DRAM DRAM DRAM DRAM DRAM AS4LC4M16 AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice. 9 AS4LC4M16 Rev. 1.1 6/05 Austin Semiconductor, Inc. CAPACITANCE2 PARAMETER SYM MAX UNIT Input Capacitance: Address Pins CI1 5pF Input Capacitance: RAS\, CAS\, WE\, OE\ CI2 7pF Input/Output Capacitance: DQ CI0 7pF AC ELECTRICAL CHARACTERISTICS5,6,7,8,9,10,11,12 (V CC = +3.3V ±0.3V) SYMBOL MIN MAX MIN MAX UNITS NOTES Access time from column address tAA 25 30 ns Column-address setup to CAS\ precharge tACH 12 15 ns Column-address hold time (referenced to RAS\) tAR 38 45 ns Column-address setup time tASC 00 ns 28 Row-address setup time tASR 00 ns 28 Column address to WE\ delay time tAWD 42 49 ns 18 Access time from CAS\ tCAC 13 15 ns 29 Column-address hold time tCAH 810 ns 28 CAS\ pulse width tCAS 8 10,000 10 10,000 ns 30, 32 CAS\ LOW to "Don't Care" during Self Refresh tCHD 15 15 ns CAS\ hold time (CBR Refresh) tCHR 810 ns 4, 31 Last CAS\ going LOW to first CAS\ to return HIGH tCLCH 55 ns 31 CAS\ to output in Low-Z tCLZ 00 ns 29 Data output hold after CAS\ LOW tCOH 33 ns CAS\ precharge time tCP 8 10 ns 13, 33 Access time from CAS\ precharge tCPA 28 35 ns 29 CAS\ to RAS\ precharge time tCRP 55 ns 31 CAS\ hold time tCSH 38 45 ns 31 CAS\ setup time (CBR Refresh) tCSR 5 5 ns 4, 28 CAS\ to WE\ delay time tCWD 28 35 ns 18, 28 WRITE command to CAS\ lead time tCWL 810 ns 31 Data-in hold time tDH 8 10 ns 19, 29 Data-in setup time tDS 0 0 ns 19, 29 Output disable tOD 0 12 0 15 ns 24, 25 Output enable time tOE 12 15 ns 20 OE\ hold time from WE\ during READ-MODIFY-WRITE cycle tOEH 810 ns 25 OE\ HIGH hold time from CAS\ HIGH tOEHC 510 ns OE\ HIGH pulse width tOEP 55 ns OE\ LOW to CAS\ HIGH setup time. tOES 45 ns Output buffer turn-off delay tOFF 0 12 0 15 ns 17, 24, 29 OE\ setup prior to RAS\ during HIDDEN REFRESH cycle tORD 00 ns DESCRIPTION -6 -5 |
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