| поискавой системы для электроныых деталей |
|
CS5560 датащи(PDF) 24 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
CS5560 датащи(HTML) 24 Page - Cirrus Logic |
|
24 / 32 page ![]() CS5560 24 DS713PP2 5/4/09 3.10 Serial Port The serial port on the CS5560 can operate in two different modes: synchronous self clock (SSC) mode & synchronous external clock (SEC) mode. 3.10.1 SSC Mode If the SMODE pin is high (SMODE = VL), the serial port operates in the SSC (Synchronous Self Clock) mode. In the SSC mode the port shifts out conversion data words with SCLK as an output. SCLK is gen- erated inside the converter from MCLK. Data is output from the SDO (Serial Data Output) pin. If CS is high, the SDO and SCLK pins will stay in a high-impedance state. If CS is low when RDY falls, the con- version data word will be output from SDO MSB first. Data is output on the rising edge of SCLK and should be latched into the external logic on the subsequent rising edge of SCLK. When all bits of the conversion word are output from the port the RDY signal will return to high. 3.10.2 SEC Mode If the SMODE pin is low (SMODE = VLR), the serial port operates in the SEC (Synchronous External Clock mode). In this mode, the user usually monitors RDY. When RDY falls at the end of a conversion, the conversion data word is placed into the output data register in the serial port. CS is then activated low to enable data output. Note that CS can be held low continuously if it is not necessary to have the SDO output operate in the high impedance state. When CS is taken low (after RDY falls) the conversion data word is then shifted out of the SDO pin by driving the SCLK pin from system logic external to the converter. If CS is held low continuously, the RDY signal will fall at the end of a conversion and the conversion data will be placed into the serial port. If the user starts a read, the user will maintain control over the serial port until the port is empty. However, if SCLK is not toggled, the converter will overwrite the conversion data at the completion of the next conversion. If CS is held low and no read is performed, RDY will rise just prior to the end of the next conversion and then fall to signal that new data has been written into the serial port. |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |