CS5560

DS713PP2

17

5/4/09

3.6 Typical Connection Diagrams

The following figure depicts the CS5560 powered from bipolar analog supplies, +2.5 V and - 2.5 V.

Figure 6. CS5560 Configured Using

VREF-

VREF+

+4.096

Voltage

Reference

(NOTE 1)

+2.5 V

SMODE

CS

RDY

CONV

MCLK

SLEEP

RST

BP/UP

1. See Section 3.3 Voltage Reference for information on required

voltage reference performance criteria.

2.Locate capacitors so as to minimize loop length.

3. The ±2.5 V supplies should also be bypassed to ground at the converter.

4. VLR and the power supply ground for the ±2.5 V should be

connected to the same ground plane under the chip.

5. SCLK and SDO may require pull-down resistors in some applications.

6. An RC input filter can be used to band limit the input to reduce noise.

Select R to be equal to the parallel combination of the feedback of the

feedback resistors 4.99k || 4.99k = 2.5k

÷÷

NOTES

-2.5 V

BUFEN

(V-) Buffers Off

(V+) Buffers On

10 µF0.1 µF

V1+

V2+

V1-

V2-

VL

VLR

DCR

+2.5 V

+3.3 V to +1.8 V

0.1 µF

0.1 µF

X7R

0.1 µF

10

-2.5 V

CS5560

TST

10

0.1 µF

AIN-

AIN+

49.9

47pF

4.99k

4700pF

C0G

49.9

47pF

4.99k

4700pF

C0G

4.99k

4.99k

-2.048 V

+2.048 V

0 V

+2.048 V

-2.048 V

0 V

VLR2

50