TMC22091 datasheet(9/60 Pages) CADEKA

9 / 60 page

PRODUCT SPECIFICATION

TMC22091/TMC22191

TTL

Chip Select. When CS is HIGH, the microprocessor interface

port, D7-0, is set to HIGH impedance and ignored. When CS is

LOW, the microprocessor can read or write parameters over

D7-0. One additional falling edge of CS is needed to move input

data to its assigned working registers.

R/W

TTL

Bus Read/Write Control. When R/W and CS are LOW, the

microprocessor can write to the control registers or CLUT over

D7-0. When R/W is HIGH and CS is LOW, it can read the

contents of any CLUT address or control register over D7-0.

RESET

TTL

Master Reset Input. Bringing RESET LOW sets the software

reset control bit, SRESET, LOW, forcing the internal state

machines to their starting states and disabling all outputs.

Bringing RESET HIGH synchronizes the internal pixel clock

(PCK = PXCK / 2) to maintain a defined pipeline delay through

the TMC22x91. If HRESET is set HIGH, the encoder is enabled

when RESET goes HIGH. If HRESET is LOW, the host restarts

the TMC22x91 by setting SRESET HIGH. RESET does not

affect the CLUT or the control registers, except SRESET.

Video Output

COMPOSITE

1 V P-P

NTSC/PAL Video. Analog output of composite D/A converter,

nominally 1.35 volt peak-to-peak into a 37.5

Ω load.

LUMA

1 V P-P

Luminance-only Video. Analog output of luminance D/A

converter, nominally 1.35 volt peak-to-peak into a 37.5

Ω load.

CHROMA

1 V P-P

Chrominance-only Video. Analog output of chrominance D/A

converter, nominally 1.35 volt peak-to-peak into a 37.5

Ω load.

Analog Interface

VREF

+1.23 V

Voltage Reference Input. External voltage reference input,

internal voltage reference output, nominally 1.235 V.

COMP

0.1

µF

Compensation Capacitor. Connection point for 0.1

µf

decoupling capacitor.

RREF

392

Ω

Current-setting Resistor. Connection point for external

current-setting resistor for D/A converters. The resistor (392

Ω)

is connected between RREF and AGND. Output video levels

are inversely proportional to the value of RREF.

JTAG Test Interface

TDI

TTL

Data Input Port. Boundary scan data input port.

TMS

TTL

Scan Select Input. Boundary scan (HIGH)/normal operation

(LOW) selector.

TCK

TTL

Scan Clock Input. Boundary scan clock.

TDO

TTL

Data Output Port. Boundary scan data output port.

Power Supply

VDD

27, 64, 81 41, 62, 95

+5 V

Positive digital power supply.

VDDA

40-43

13-17

+5 V

Positive analog power supply.

DGND

10, 26, 65,

42, 61, 76,

0.0 V

Digital Ground.

AGND

32, 34, 36,

4, 6, 9,

100

0.0 V

Analog Ground.

Pin Descriptions (continued)

Pin Name

Pin Number

Value

Pin Function Description

84-Lead

PLCC

100-Lead

MQFP

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