SPT8100 datasheet(5/10 Pages) CADEKA

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SPT8100

initialization phase until RDY is deasserted. Note that,

although typically the device is initialized when power is

first applied, the initialization is only started when the RS is

asserted; there is no “power-on-reset” circuitry on chip. RS

may be held low for an indefinite period of time. While RS is

low, RDY will remain high. After RS is returned to high, RDY

will go low for the duration of the calibration.

PROGRAMMABLE GAIN AMPLIFIER

The programmable gain amplifier (PGA) precedes the

ADC inputs. The differential inputs, which are resistive, are

at pins VIN+ and VIN–.The maximum input range is 5 V

peak-to-peak differential (2.5 V single-ended). To achieve

maximum overall system noise performance, the source

driving these inputs needs to be as low-noise and as low-

jitter as possible, while maintaining the required distortion

performance. In addition, the driving source must be low

impedance to maintain the accuracy of the PGA gain.

The internal 0 dB analog signal level and ADC full-scale

output level is 5 V peak-to-peak differential (2.5 V single-

ended). The PGA may be used to provide gain for an input

less than 5 V peak-to-peak differential.

The gain of the PGA can be programmed using a three-bit

control, available at pins GS0 to GS2. See table I. Note that

the input resistance is a function of the gain setting.

Table I – PGA Gain Control

PGA

Input

V/V

3 dB

GS2 GS1 GS0

Gain Resistance Gain

LSBRMS

(dB)

Ω

Ω)

5.57

1.4

2.9

4.65

1.40

1.5

5.8

3.97

1.95

1.6

11.8

2.23

3.9

2.0

14.8

1.66

5.5

2.3

17.5

1.25

7.5

5.5

2.6

19.5

1.00

9.5

2.8

Forbidden

TYPICAL INTERFACE CIRCUIT

ANALOG INPUT DRIVER

The differential analog inputs (VIN+, VIN–) have a resistive

input impedance of 1 k

Ω minimum. For best performance,

the input source should be a differential input, as shown in

figure 2, typical interface circuit. The SPT8100 provides its

own common-mode voltage on the pin marked VCM. Out-

put drive capability of VCM is a maximum of 47 µA (50 kΩ to

ground).

The SPT8100 application note (AN8100) shows an ex-

ample of two modes of driving the SPT8100. One mode is

through a transformer and the other is through a single-to-

differential converter. In all cases, both inputs VIN+ and

VIN– must be kept within the input common-mode range

(1.15 V to 3.65 V).

BIASC CONNECTION

An external capacitor, CEXT on the BIASC pin, is used only

for noise filtering of an internal voltage associated with the

references. Its value is not critical: 1 µF in parallel with

0.01 µF is recommended.

BIASR CONNECTION

As shown in the typical interface circuit, REXT is needed to

connect between BIASR to ground. This resistor ranges

from 800

Ω to 2.5 kΩ. The proper selection of REXT is a

function of the sample rate and input frequency. Nominally,

at 5 MSPS, REXT=1.43 kΩ is recommended. If linearity for

large signal levels at an analog bandwidth of 2 MHz is criti-

cal, the value should be decreased to REXT=1.24 kΩ; and

for even higher-frequency analog inputs, REXT=1.0 kΩ can

be used. At lower sample rates (for example 2 MSPS),

and lower analog input frequencies, the value may be in-

creased to REXT=2 kΩ. (Refer to the typical interface circuit

table in figure 2b.)

POWER SUPPLIES AND GROUNDING

The SPT8100 requires three power supplies: analog AVDD,

digital DVDD and output supply OVDD. This device works

best if all three supplies are coming from the analog supply

side of the system as shown in the typical interface circuit

(figure 2a).

Note, in figure 2a, that the supplies to the logic interface

circuit and the OVDD are separate from each other. In a

case where the +A3.3/5 V supply is not available, try to

implement the design as close as possible to that shown

in figure 2b. Place the ferrite bead (FB1) as close to the

device as possible. To avoid latch-up, the delta between

all three grounds must stay with 100 mV; this includes

transients. (Refer to the absolute maximum ratings

specifications.)

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