Laser Printer System Frequency Synthesizer
CY24242
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07268 Rev. *B
Revised January 19, 2005
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Reduces measured EMI by as much as 10 dB
• Four skew-controlled copies of CPU output
• Four skew-controlled copies of SDRAM output
• One copy of 14.31818-MHz Reference output
• One copy of 48-MHz USB clock (not spread)
• Selectable SSFTG modulation width
• Available in 28-pin SSOP (209 mil)
Key Specifications
Supply Voltage:
VDDCORE: ........................................................... 3.3V±10%
VDDC: ............................................... 3.3V±10% or 2.5V±5%
VDDS: ............................................... 3.3V±10% or 2.5V±5%
VDDU: ............................................... 3.3V±10% or 2.5V±5%
CPU Clock Cycle to Cycle Jitter: ................................ 250 ps
USBCLK Long term Jitter:....................................... ± 500 ps
CPU0:3 Clock Skew: .................................................. 250 ps
CPU, SDRAM Output on Resistance: ............................. 15
Ω
Logic inputs have 250K-ohm pull-up resistors
Notes:
1. All clock output loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section.
2. Signals marked with [*] have internal pull-up resistors
3. Signal marked with[^] has internal pull-down resistors.
Table 1. Pin Selectable Frequency[1]
FS1 FS0
CPU(0:3),
SDRAM(0:3)
USBCLK
0
0
133.3 MHz
48 MHz
0
1
100 MHz
48 MHz
1
0
66.6 MHz
48 MHz
1
1
50 MHz
48 MHz
Table 2. Spread Characteristics.
SSON#
SS%1
SS%0
CPU(0:3),
SDRAM(0:3)
0
0
0
–0.5%
0
0
1
–1.0%
0
1
0
–2.5%
011
–3.75%
1
0
0
0 (off)\
101
0 (off)
110
0 (off)
111
0 (off)
Block Diagram
Pin Configuration
REF
XTAL
PLL Ref Freq
PLL 1
X2
X1
CPU0:3
SDRAM0:3
USBCLK
PLL 2
OSC
FS0
FS1
SSON#
USBCLKEN
SS%0
SS%1
SDEN
VDDCORE
REF
GND
X1
X2
SDRAM3
SDRAM2
VDDS
SDRAM1
SDRAM0
GND
VDDCORE
*SDEN
*SS%0
USBCLKEN
GND
USBCLK
VDDU
CPU0
CPU1
VDDC
CPU2
CPU3
GND
SS%1*
SSON#^
FS1*
FS0*
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
[2, 3]
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