CY24242PVC datasheet(7/10 Pages) CYPRESS

7 / 10 page

CY24242

Document #: 38-07268 Rev. *B

Page 7 of 10

AC Electrical Characteristics

TA = 0°C to +70°C, VDD = VDDQ3 = 2.5V ± 5%, fXTL = 14.31818 MHz

AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the

clock output.

CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF, VDDC = 2.5V)

Parameter

Description

Test Condition/Comments

CPU = 66 MHz

CPU = 100 MHz

Unit

Min. Typ. Max. Min. Typ. Max.

Period

Measured on rising edge at 1.25V

–

15.5

–

10.5

High Time

Duration of clock cycle above 2.0V

5.2

–

3.0

–

Low Time

Duration of clock cycle below 0.4V

–

2.8

–

Output Rise Edge Rate Measured from 0.4V to 2.0V

0.4

–

3.2

0.4

–

3.2

V/ns

Output Fall Edge Rate

Measured from 2.0V to 0.4V

0.4

–

3.2

0.4

–

3.2

V/ns

Duty Cycle

Measured on rising and falling edge at

1.25V

–

tJC

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.25V.

Maximum difference of cycle time

between two adjacent cycles.

–

250

–

250

tSK

Output Skew

Measured on rising edge at 1.25V

–

250

–

250

fST

Frequency Stabilization

from Power-up (cold

start)

Assumes full supply voltage reached

within 1 ms from power-up. Short

cycles exist prior to frequency stabili-

zation.

–

–3–

–3

AC Output Impedance

Average value during switching

transition. Used for determining series

termination value.

–

20–

–

20–

Ω

SDRAM Clock Outputs, SDRAM0:3 (Lump Capacitance Test Load = 30 pF, VDDC = 2.5V)

Parameter

Description

Test Condition/Comments

CPU = 66 MHz

CPU = 100 MHz

Unit

Min. Typ. Max. Min. Typ. Max.

Period

Measured on rising edge at 1.25V

–

15.5

–

10.5

High Time

Duration of clock cycle above 2.0V

5.2

–

3.0

–

Low Time

Duration of clock cycle below 0.4V

–

2.8

–

Output Rise Edge Rate Measured from 0.4V to 2.0V

0.4

–

3.2

0.4

–

3.2

V/ns

Output Fall Edge Rate Measured from 2.0V to 0.4V

0.4

–

3.2

0.4

–

3.2

V/ns

Duty Cycle

Measured on rising and falling edge at

1.25V

–

tJC

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.25V.

Maximum difference of cycle time

between two adjacent cycles.

–

250

–

250

tSK

Output Skew

Measured on rising edge at 1.25V

–

250

300

–

250

350

fST

Frequency Stabilization

from Power-up (cold

start)

Assumes full supply voltage reached

within 1 ms from power-up. Short cycles

exist prior to frequency stabilization.

–

–3–

–3

AC Output Impedance Average value during switching

transition. Used for determining series

termination value.

–20

–

–20

–

Ω

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