STA2500D datasheet(26/57 Pages) STMICROELECTRONICS

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General specification

STA2500D

26/57

Doc ID 16067 Rev 1

6.3

Class 1 operation

The STA2500D supports operation at Class 1 output power levels with the use of an

external PA. The operation of the external PA and antenna switch are controlled by the

following signals:

If Class 1 functionality is enabled through SW parameter download, then these 6 control

signals are available on the pins as indicated in Table 21 and Table 22.

Configuration 2 allows to deploy the STA2500D in Class 1 mode, still maintaining the

necessary control signals to coexist and cooperate with a WLAN transceiver. The

handshake between the STA2500D and a WLAN device happens in this case through other

BT_GPIO pins.

6.4

Power-up

The BT_RESETN pin should be active while powering up BT_VDD_HV and should stay

active at least two cycles of the low power clock (BT_LP_CLK) after power-up is completed.

The time between the STA2500D making BT_CLK_REQ_OUT_x active and the platform

providing a stable clock should maximally be 15 ms.

Table 20.

Output power: class 1 control signals

Control signal name

Function

PAEN

PA enable (active during TX slot)

PA_VAL0

Bit 0 of the power level delivered by the PA

PA_VAL1

Bit 1 of the power level delivered by the PA

RXEN

LNA enable (if present)

AntSw

Control of the antenna switch

edr_mode

Indication to PA whether TX is EDR or BR

Table 21.

Output power: class 1 device pin configuration (depending on SW

parameter download)

Function

SW configuration 1

SW configuration 2

PAEN

BT_HOST_WAKEUP

BT_GPIO_16

PA_VAL0

BT_GPIO_0

BT_GPIO_10

PA_VAL1

BT_CLK_REQ_IN_1

BT_GPIO_9

RXEN

BT_CLK_REQ_IN_2

BT_GPIO_8

AntSw

(BT_GPIO_11)

BT_GPIO_11

Table 22.

Output power: class 1 device pin configuration (depending on SW

parameter download)

Function

SW configuration a

SW configuration b

SW configuration c

edr_mode

BT_CLK_REQ_OUT_1

BT_CLK_REQ_OUT_2

not available on a pin

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