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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STA2500D датащи(PDF) 16 Page - STMicroelectronics |
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STA2500D датащи(HTML) 16 Page - STMicroelectronics |
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16 / 57 page  Pinout STA2500D 16/57 Doc ID 16067 Rev 1 4.2 HW configuration of the STA2500D By means of the three configuration pins, one can select the Host interface (UART or SPI) and clock request signal polarity to be used at startup. The available combinations of Host interface and protocol are illustrated in Table 14 (where ‘1’ = BT_VIO_A and ‘0’ = BT_VSSDIG). Additionally, the polarity of the BT_CLK_REQ signals can be programmed through the same pins. The polarity of the BT_CLK_REQ_IN and BT_CLK_REQ_OUT signals is further described in Section 6.8. BT_VDD_D G2 Internal supply decoupling/Regulator output. Need 220nF decoupling capacitor to BT_VSSDIG. -- - BT_VDD_DSM B7 Internal supply decoupling/Regulator output. Need 220nF decoupling capacitor to BT_VSSANA. -- - BT_VDD_N C7 Internal supply decoupling/Regulator output. Need 220nF decoupling capacitor to BT_VSSANA. -- - BT_VDD_RF A1 Internal supply decoupling/Regulator output. Need 220nF decoupling capacitor to BT_VSSRF. -- - Other pins BT_TEST1 B5 Test pin I/O Input (8) Input (8) BT_TEST2 A6 BT_AF_PRG E5 Test pin (Leave unconnected)(9) I/O Open Open 1. Pin behaviour during HW reset (BT_RESETN low). 2. Pin behaviour immediately after HW reset and internal chip initialization, but before SW parameter download. 3. See also pin BT_VDD_CLD in Table 13. 4. Reconfigurable I/O pin.The functionality of these I/Os can be configured through software parameter download (see Section 7.5). 5. Should be strapped to BT_VSSDIG if not used. 6. JTAG mode. 7. Described in Section 4.3. 8. To be strapped to BT_VSSANA. 9. Pin is ST - reserved for test function and it must be soldered to an isolated pad (not connected to anything, just floating). Table 13. The STA2500D pin list (functional and supply) (continued) Name Pin # Description Type Reset(1) Default(2) after reset |
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