ABSOLUTE MAXIMUM RATINGS

POWER DISSIPATION RATINGS

(1)

TPS737xx

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PRODUCT

(2)

TPS737xxyyyz

YYY is package designator.

Z is package quantity.

(1)

For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2)

Most output voltages of 1.25V and 1.3V to 5.0V in 100mV increments are available on a quick-turn basis using innovative factory

package-level programming. Minimum order quantities apply; contact factory for details and availability.

(3)

For fixed 1.20V operation, tie FB to OUT.

over operating free-air temperature range unless otherwise noted

(1)

PARAMETER

TPS737xx

UNIT

–0.3 to +6.0

V

–0.3 to +6.0

V

–0.3 to +5.5

V

–0.3 to +6.0

V

Peak output current

Internally limited

Output short-circuit duration

Indefinite

Continuous total power dissipation

See Dissipation Ratings Table

–55 to +150

°C

Storage temperature range

–65 to +150

°C

ESD rating, HBM

2

kV

ESD rating, CDM

500

V

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics

is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

DERATING FACTOR

BOARD

PACKAGE

POWER RATING

POWER RATING

POWER RATING

DCQ

15°C/W

53°C/W

18.9mW/°C

1.89W

1.04W

0.76W

DCQ

15°C/W

45°C/W

22.2mW/°C

2.22W

1.22W

0.89W

DRB

1.2°C/W

40°C/W

25.0mW/°C

2.50W

1.38W

1.0W

(1)

See Power Dissipation in the Applications section for more information related to thermal design.

(2)

The JEDEC Low-K (1s) board design used to derive this data was a 3-inch × 3-inch, 2-layer board with 2-ounce copper traces on top of

the board.

(3)

The JEDEC High-K (2s2p) board design used to derive this data was a 3-inch x 3-inch, multilayer board with 1-ounce internal power and

ground planes and 2-ounce copper traces on the top and bottom of the board.

(4)

Based on preliminary thermal simulations.

2

Submit Documentation Feedback

Copyright © 2006–2009, Texas Instruments Incorporated