CDCE62002 datasheet(26/49 Pages) TI

26 / 49 page

Device Control

Device

OFF

Active Mode

Power ON

Reset

Power Down

Sync

VCO

CAL

Power

Applied

Delay

Finished

Power Down = ON

Sync = ON

Sync = OFF

PLLRESET= ON

External Control Pins

CDCE62002

SCAS882A – JUNE 2009 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com

Figure 19 provides a conceptual explanation of the CDCE62002 Device operation. Table 11 defines how the

device behaves in each of the operational states.

Figure 19. CDCE62002 Device State Control Diagram

Table 11. CDCE62002 Device State Definitions

Output

SPI Port

PLL

State

Device Behavior

Entered Via

Exited Via

Divider

Buffer

Status

Power-On

After device power supply reaches

Power applied to the device or

Power On Reset and EEPROM

OFF

Disabled

OFF

Reset

approximately 2.35V, the contents of

upon exit from Power Down State

loading delays are finished OR the

EEPROM are copied into the Device

via the PD pin set HIGH.

PD pin is set LOW.

Registers, thereby initializing the device

hardware .

VCO CAL

The voltage controlled oscillator is

Delay process in the Power-On

Calibration Process in completed

Enabled

Disabled

OFF

calibrated based on the PLL settings

Reset State is finished or

and the incoming reference clock. After

PLLRESET=ON

the VCO has been calibrated, the device

enters Active Mode automatically.

Active Mode

Normal Operation

CAL Done (VCO calibration

Power Down or PLLRESET=ON

Enabled

Disabled

Disabled or

process finished) or Sync = OFF

Enabled

(from Sync State).

Enabled

Power Down

Used to shut down all hardware and

PD pin is pulled LOW.

PD pin is pulled HIGH.

Disabled

Resets the device after exiting the

Power Down State. Therefore, the

EEPROM contents will eventually be

copied into RAM after the Power Down

State is exited.

Sync

Sync synchronizes both outputs dividers

Sync Bit in device register 2 bit 8

Sync bit in device register 2 bit 8 is

Enabled

Disabled

so that they begin counting at the same

is set LOW

set HIGH

time

Power Down (PD)

When pulled LOW, PD activates the Power Down state which shuts down all hardware and resets the device.

Restoring PD high will cause the CDCE62002 to exit the Power Down State. This causes the device to behave

as if it has been powered up including copying the EEPROM contents into RAM. PD pin also has a shadowed

PD bit residing in Register 2 Bit 7. When asserted Low it puts the device in Power Down Mode, but it does not

load the EEPROM when the bits is disserted.

NOTE:

Submit Documentation Feedback

Product Folder Link(s): CDCE62002

CDCE62002 датащи(PDF) 26 Page - Texas Instruments

CDCE62002 датащи(HTML) 26 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

датащи скачать

ссылки URL