CDCE62002 datasheet(21/49 Pages) TI

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Writing to the CDCE62002

SPI_CLK

Bit0

Bit1

Bit29

Bit30

Bit31

SPI_LE

SPI_MOSI

Reading from the CDCE62002

SPI_ CLK

SPI_ MOSI

SPI_ MISO

SPI_LE

Bit

Bit0

Bit1

Bit2

Bit

Writing to EEPROM

CDCE62002

www.ti.com.............................................................................................................................................................. SCAS882A – JUNE 2009 – REVISED JULY 2009

Figure 17 illustrates a Write to RAM operation. Notice that the latching of the first data bit in the data stream (Bit

0) occurs on the first rising edge of SPI_CLK after SPI_LE transitions from a high to a low. For the CDCE62002,

data transitions occur on the falling edge of SPI_CLK. A rising edge on SPI_LE signals to the CDCE62002 that

the transmission of the last bit in the stream (Bit 31) has occurred.

Figure 17. CDCE62002 SPI Write Operation

Figure 18 shows how the CDCE62002 executes a Read Command. The SPI master first issues a Read

Command to initiate a data transfer from the CDCE62002 back to the host (see Table 6). This command

specifies the address of the register of interest. By transitioning SPI_LE from a low to a high, the CDCE62002

resolves the address specified in the appropriate bits of the data field. The host drives SPI_LE low and the

CDCE62002 presents the data present in the register specified in the Read Command on SPI_MISO.

Figure 18. CDCE62002 Read Operation

After the CDCE62002 detects a power-up and completes a reset cycle, it copies the contents of the on-board

EEPROM into the Device Registers. Therefore, the CDCE62002 initializes into a known state predefined by the

user. The host issues one of two special commands shown in Table 6 to copy the contents of Device Registers 0

through 1 into EERPOM. They include:

•

Copy RAM to EEPROM – Unlock, Execution of this command can happen many times.

•

Copy RAM to EEPROM – Lock: Execution of this command can happen only once; after which the EEPROM is permanently locked.

After either command is initiated, power must remain stable and the host must not access the CDCE62002 for at

least 50 ms to allow the EEPROM to complete the write cycle and to avoid the possibility of EEPROM corruption.

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