May 2007

ASM3P623S05/09A/B

rev 0.3

Notice: The information in this document is subject to change without notice.

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200 Campbell, CA 95008

• Tel: 408-879-9077 • Fax: 408-879-9018

www.pulsecoresemi.com

Timing-Safe™ Peak EMI reduction IC

General Features

•

Clock distribution with Timing-Safe™ Peak EMI

Reduction

•

Input frequency range: 20MHz - 50MHz

•

Zero input - output propagation delay

•

Low-skew outputs

• Output-output skew less than 250pS

• Device-device skew less than 700pS

•

Less than 200pS cycle-to-cycle jitter is compatible

with Pentium

•

Available in 16pin, 150mil SOIC, 4.4mm TSSOP

(ASM3P623S09A/B), and in 8pin, 150 mil SOIC,

4.4mm TSSOP Packages (ASM3P623S05A/B)

•

3.3V Operation

•

Advanced CMOS technology

•

The First True Drop-in Solution

Functional Description

ASM3P623S05/09A/B is a versatile, 3.3V zero-delay buffer

designed to distribute high-speed Timing-Safe™ clocks

with Peak EMI Reduction. ASM3P623S09A/B accepts one

reference input and drives out nine low-skew clocks. It is

available in a 16pin Package. The ASM3P623S05A/B is

the eight-pin version and accepts one reference input and

drives out five low-skew clocks.

All parts have on-chip PLLs that lock to an input clock on

the CLKIN pin. The PLL feedback is on-chip and is

obtained from the CLKOUT pad, internal to the device.

Multiple ASM3P623S05/09A/B devices can accept the

same input clock and distribute it. In this case, the skew

between the outputs of the two devices is guaranteed to be

less than 700pS.

All outputs have less than 200pS of cycle-to-cycle jitter.

The input and output propagation delay is guaranteed to be

less than ±350pS, and the output-to-output skew is

guaranteed to be less than 250pS.

Refer

Table”

for

deviations

and

Input-Output

Skew

for

ASM3P623S05A/B and ASM3P623S09A/B devices

The

ASM3P623S05A/B

and

ASM3P623S09A/B

are

available in two different packages, as shown in the

ordering information table.

Block Diagram

ASM3P623S09A/B

PLL

MUX

CLKOUT

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

Select Input

Decoding

S2

S1

CLKIN

PLL

CLKOUT

CLK1

CLK2

CLK3

CLK4

ASM3P623S05A/B

CLKIN