TMS320VC5410 datasheet(21/79 Pages) TI

21 / 79 page

TMS320VC5410

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS075D – OCTOBER 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

multichannel buffered serial ports (continued)

The CPU and DMA can move data to and from the McBSPs and can synchronize transfers based on McBSP

interrupts, event signals, and status flags. The DMA is capable of handling data movement between the

McBSPs and memory with no intervention from the CPU.

In addition to the standard serial-port functions, the McBSP provides programmable clock and frame

synchronization generation. Among the programmable functions are:

D Frame synchronization pulse width

D Frame period

D Frame synchronization delay

D Clock reference (internal vs. external)

D Clock division

D Clock and frame synchronization polarity

The on-chip companding hardware allows compression and expansion of data in either

µ-law or A-law format.

When companding is used, transmit data is encoded according to specified companding law and received data

is decoded to 2s complement format.

The McBSP allows the multiple channels to be independently selected for the transmitter and receiver. When

the multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In

using TDM data streams, the CPU may only need to process a few of them. Thus, to save memory and bus

bandwidth, multichannel selection allows independent enabling of particular channels for transmission and

reception. Up to 32 channels in a bit stream of up to 128 channels can be enabled.

The clock-stop mode (CLKSTP) in the McBSP provides compatibility with the serial peripheral interface (SPI)

protocol. Clock-stop mode works with only single-phase frames and one word per frame. The word sizes

supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is

configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a

slave.

The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum frequency is CPU

clock frequency divided by 2.

hardware timer

The ’VC5410 device features a 16-bit timing circuit with a 4-bit prescaler. The timer counter is decremented by

one every CPU clock cycle. Each time the counter decrements to 0, a timer interrupt is generated. The timer

can be stopped, restarted, reset, or disabled by specific status bits.

clock generator

The clock generator provides clocks to the ’VC5410 device, and consists of an internal oscillator and a

phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided

by using a crystal resonator with the internal oscillator, or from an external clock source. The reference clock

input is then divided by two (DIV mode) to generate clocks for the ’VC5410 device, or the PLL circuit can be

used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor,

allowing use of a clock source with a lower frequency than that of the CPU.The PLL is an adaptive circuit that,

once synchronized, locks onto and tracks an input clock signal.

When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input

signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then,

other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the

’VC5410 device.

TMS320VC5410 датащи(PDF) 21 Page - Texas Instruments

TMS320VC5410 датащи(HTML) 21 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

датащи скачать

ссылки URL