TMS320VC5410 datasheet(13/79 Pages) TI

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TMS320VC5410

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS075D – OCTOBER 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

relocatable interrupt vector table

The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that

the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the

code at the vector location. Four words, either two 1-word instructions or one 2-word instruction, are reserved

at each vector location to accommodate a delayed branch instruction which allows branching to the appropriate

interrupt service routine without the overhead.

At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However,

these vectors can be remapped to the beginning of any 128-word page in program space after device reset.

This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate

128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new

128-word page.

NOTE: The hardware reset (RS) vector cannot be remapped because the hardware reset loads the IPTR

with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.

extended program memory

The ’VC5410 uses a paged extended memory scheme in program space to allow access of up to 8192K of

program memory. In order to implement this scheme, the ’VC5410 includes several features which are also

present on ’C548/549:

D Twenty-three address lines, instead of sixteen

D An extra memory-mapped register, the XPC

D Six extra instructions for addressing extended program space

Program memory in the ’VC5410 is organized into 128 pages that are each 64K in length, as shown in Figure 2.

00 0000

Page 0

64K

Words

01 0000

Page 1

64K

Words

02 0000

Page 2

64K

Words

. . .

7F 0000

Page 127

64K

Words

00 FFFF

01 FFFF

02 FFFF

. . .

7F FFFF

XPC = 0

XPC = 1

XPC = 2

XPC=127

Figure 2. Extended Program Memory

(On-Chip RAM Not Mapped in Program Space and Data Space, OVLY = 0)

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