TMS320VC5402 datasheet(43/68 Pages) TI

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TMS320VC5402

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

memory and parallel I/O interface timing (continued)

timing requirements for a

parallel I/O port read (IOSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 15)

MIN

MAX

UNIT

ta(A)IO

Access time, read data access from address valid

3H–7

ta(ISTRBL)IO

Access time, read data access from IOSTRB low

2H–7

tsu(D)IOR

Setup time, read data before CLKOUT high

th(D)IOR

Hold time, read data after CLKOUT high

th(ISTRBH-D)R

Hold time, read data after IOSTRB high

† Address and IS timings are included in timings referenced as address.

switching characteristics over recommended operating conditions for a

parallel I/O port read

(IOSTRB = 0)† (see Figure 15)

PARAMETER

MIN

MAX

UNIT

td(CLKL-A)

Delay time, CLKOUT low to address valid

–2

td(CLKH-ISTRBL)

Delay time, CLKOUT high to IOSTRB low

–2

td(CLKH-ISTRBH)

Delay time, CLKOUT high to IOSTRB high

–2

th(A)IOR

Hold time, address after CLKOUT low

† Address and IS timings are included in timings referenced as address.

R/W

IOSTRB

D[15:0]

A[19:0]

CLKOUT

th(A)IOR

td(CLKH-ISTRBH)

th(D)IOR

tsu(D)IOR

ta(A)IO

td(CLKH-ISTRBL)

td(CLKL-A)

ta(ISTRBL)IO

th(ISTRBH-D)R

NOTE A: A[19:16] are always driven low during accesses to I/O space.

Figure 15. Parallel I/O Port Read (IOSTRB = 0)

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