TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

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POST OFFICE BOX 655303

features

625 KSPS at 3 V

Parallel Interface

applications

description

The TLV571 is an 8-bit data acquisition system

that combines a high-speed 8-bit ADC and a

parallel interface. The device contains two on-chip control registers allowing control of software conversion start

and power down via the bidirectional parallel port. The control registers can be set to a default mode using a

dummy RD while WR is tied low allowing the registers to be hardware configurable.

The TLV571 operates from a single 2.7-V to 5.5-V power supply. It accepts an analog input range from 0 V to

12 mW with a 3-V supply or 35 mW with a 5-V supply. The device features an auto power-down mode that

automatically powers down to 1 mA 50 ns after conversion is performed. In software power-down mode, the

ADC is further powered down to only 10

µA.

Very high throughput rate, simple parallel interface, and low power consumption make the TLV571 an ideal

choice for high-speed digital signal processing.

AVAILABLE OPTIONS

PACKAGE

TA

24 TSSOP

(PW)

24 SOIC

(DW)

–40

°C to 85°C

TLV571IPW

TLV571IDW

Copyright

© 2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NC – No internal connection

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24

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13

CS

WR

RD

CLK

DGND

DVDD

INT/EOC

DGND

DGND

D0

D1

D2

NC

AIN

AVDD

AGND

REFM

REFP

CSTART

A1/D7

A0/D6

D5

D4

D3

DW OR PW PACKAGE

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