TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

5

POST OFFICE BOX 655303

detailed description (continued)

Table 1. Conversion Modes

START OF

CONVERSION

OPERATION

COMMENTS – FOR INPUT

Hardware start

(CSTART)

CR0.D5 = 0

• Repeated conversions from AIN

• CSTART falling edge to start sampling

• CSTART rising edge to start conversion

• If in INT mode, one INT pulse generated after each conversion

• If in EOC mode, EOC will go high to low at start of conversion, and return high

at end of conversion.

CSTART rising edge must be applied

a minimum of 5 ns before or after CLK

rising edge.

Software start

CR0.D5 = 1

• Repeated conversions from AIN

• WR rising edge to start sampling initially. Thereafter, sampling occurs at the

rising edge of RD.

• Conversion begins after 6 clocks after sampling has begun. Thereafter, if in INT

mode, one INT pulse generated after each conversion

• If in EOC mode, EOC will go high to low at start of conversion and return high at

end of conversion.

With external clock, WR and RD rising

edge must be a minimum 5 ns before

or after CLK rising edge.

configure the device

The device can be configured by writing to control registers CR0 and CR1.

Table 2. TLV571 Programming Examples

REGISTER

INDEX

D5

D4

D3

D2

D1

D0

COMMENT

REGISTER

D7

D6

D5

D4

D3

D2

D1

D0

COMMENT

EXAMPLE1

CR0

0

0

0

0

0

0

0

0

Normal, INT OSC

CR1

0

1

0

0

0

0

0

0

Binary

EXAMPLE2

CR0

0

0

0

1

1

1

0

0

Power down, EXT OSC

CR1

0

1

0

0

0

0

1

0

2’s complement output

power down

The TLV571 offers two power down modes, auto power down and software power down. This device will

automatically proceed to auto power down mode if RD is not present one clock after conversion. Software power

Table 3. Power Down Modes

PARAMETERS/MODES

AUTO POWER DOWN

SOFTWARE POWER DOWN

(CS = DVDD)

Maximum power down dissipation current

1 mA

10

µA

Comparator

Power down

Power down

Clock buffer

Power down

Power down

Control registers

Saved

Saved

Minimum power down time

1 CLK

2 CLK

Minimum resume time

1 CLK

2 CLK