Datasheet

ZADCS0882/0842/0822 Family

Copyright © 2008, ZMD AG, Rev. 1.1

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Information furnished in this publication is preliminary and subject to changes without notice.

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ple/hold may drop to noticeable affect the conversion

result.

Further detailed timing information on the digital interface

is provided in Table 8 and Figure 15.

Output Code Format

ZADCS08x2 family devices do all support unipolar and

bipolar operation modes. The digital output code is

straight binary in unipolar mode. It ranges from 0x00 for

an input voltage difference of 0V to 0xFF for an input

code transition (0x00 à 0x01) occurs at a voltage equiva-

See also Figure 16 for details.

In bipolar mode a two’s complement coding is applied.

Code transitions occur again halfway between successive

integer LSB values. The transfer function is shown in

Figure 17.

Table 8: Timing Characterisitics (VDD = +2.7V to + 5.25V;

Parameter

Symbol Conditions

Min

Typ

Max

Unit

SCLK Periode

303.0

ns

SCLK Pulse Width High

151.5

ns

SCLK Pulse Width Low

151.5

ns

DIN to SCLK Setup

30

ns

DIN to SCLK Hold

10

ns

nCS Fall to SCLK Setup

30

ns

SCLK Fall to

DOUT & SSTRB Hold

10

ns

SCLK Fall to

DOUT & SSTRB Valid

40

ns

nCS Rise to

DOUT & SSTRB Disable

10

60

ns

nCS Fall to

DOUT & SSTRB Enable

60

ns

nCS Pulse Width High

100

ns

nCS

SCLK

DIN

SSTRB

DOUT

Figure 15: Detailed Timing Diagram