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ZADCS0882 датащи(PDF) 7 Page - Zentrum Mikroelektronik Dresden AG |
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ZADCS0882 датащи(HTML) 7 Page - Zentrum Mikroelektronik Dresden AG |
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7 / 20 page ![]() Datasheet ZADCS0882/0842/0822 Family Copyright © 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. 7/20 1.5 Electrical Characteristics 1.5.1 General Parameters (VDD = +2.7V to + 5.25V; fSCLK = 3.3MHz (50% duty cycle); 11 clocks/conversion cycle (300 ksps); VREF = 2.500V applied to VREF pin; qOP = qOPmin … qOPmax) Parameter Symbol Conditions Min Typ Max Unit DC Accuracy Resolution 8 Bits Relative Accuracy INL ZADCS0882 / ZADCS0882V ZADCS0842 / ZADCS0842V ZADCS0822 / ZADCS0822V ± 0.25 LSB No Missing Codes NMC 8 Bits Differential Nonlinearity DNL ZADCS0882 / ZADCS0882V ZADCS0842 / ZADCS0842V ZADCS0822 / ZADCS0822V ± 0.25 LSB Offset Error ± 0.25 ± 1.0 LSB Gain Error ± 0.25 ± 1.0 LSB Gain Temperature Coefficient ± 0.25 ppm/°C Dynamic Specifications (10kHz sine-wave input, 0V to 2.500Vpp, 300ksps, 3.3MHz external clock) Signal-to-Noise + Distortion Ratio SINAD 49 dB Total Harmonic Distortion THD Up to the 5 th harmonic -66 dB Spurious-Free Dynamic Range SFDR 64 dB Small-Signal Bandwidth -3dB roll off 3.8 MHz Conversion Rate Sampling Time (= Track/Hold Acquisition Time) tACQ Ext. Clock = 3.3MHz, 2.5 clocks/ acquisi- tion 0.758 µs Ext. Clock = 3.3MHz, 8 clocks/ conver- sion 2.43 µs Conversion Time tCONV Int. Clock = 3.3MHz +/- 12% tolerance 2.20 2.80 µs Aperture Delay 30 ns Aperture Jitter < 50 ps External Clock Frequency 0.1 3.3 MHz Internal Clock Frequency 2.81 3.3 3.58 MHz Analog Inputs Unipolar, COM = 0V 0 to VREF Input Voltage Range, Single- Ended and Differential Bipolar, COM = VREF/2 ± VREF / 2 V Input Capacitance 16 pF |
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