Chapter 1: DC and Switching Characteristics of HardCopy III Devices

1–21

I/O Timing Model

© December 2008

Altera Corporation

HardCopy III Device Handbook, Volume 3

Duty Cycle Distortion (DCD) Specifications

Table 1–32 lists the worst case DCD for HardCopy III devices. Detailed information on

duty cycle distortion are published after characterization.

I/O Timing Model

The I/O timing specifications for HardCopy III devices will be available in a future

revision of the DC and Switching Characteristics chapter in volume 3 of the HardCopy III

Device Handbook.

Glossary

Table 1–33 shows the glossary for this chapter.

Table 1–32. Duty Cycle Distortion on HardCopy III I/O Pins – Preliminary (Note 1), (2)

Symbol

Min

Max

Unit

Output Duty Cycle

45

55

%

Notes to Table 1–32:

(1) Preliminary DCD specification applies to clock outputs from PLLs, global clock tree, IOE driving dedicated, and

general purpose I/O pins.

(2) Detailed DCD specifications pending silicon characterization.

Table 1–33. Glossary Table

Letter

Subject

Definitions

A

——

B

——

C

——

D

Differential I/O

Standards

Figure 1–2. Receiver Input Waveforms

Transmitter Output Waveforms

E

——

F

f

HSCLK

HIGH-SPEED I/O Block: High-speed receiver/transmitter input and output clock frequency.

f

HSDR

HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (f

non-DPA.

f

HSDRDPA

HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (f

G

——

H

——

Single-Ended Waveform

Differential Waveform

Ground

p

− n = 0 V

Single-Ended Waveform

Differential Waveform

Ground

p

− n = 0 V