CDCR81

DIRECT RAMBUS

™ CLOCK GENERATOR

SCAS606B – NOVEMBER 1998 – REVISED NOVEMBER 1999

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POST OFFICE BOX 655303

Direct RAMBUS Memory Systems for an

600-MHz Data Transfer Rate

Rambus Channel With an External System

or Processor Clock

Power for Mobile and Other

Power-Sensitive Applications

120-mW at 300 MHz (Typ)

Package (DBQ)

33 MHz to 100 MHz

Capability to Reduce EMI

Synthesizers CDC925, CDC924, CDC922

and CDC921

description

The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus

memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system

or processor clock. It is designed to support Direct Rambus memory on desktop, workstation, server and mobile

PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus memory

applications.

The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to

enable synchronous communication between the Rambus channel and ASIC clock domains. In a Direct

Rambus memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the

DRCG and memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK

to RDRAMs and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK

frequencies by ratios M and N such that PCLK/M = SYNCLK/N, where SYNCLK = BUSCLK/4. The DRCG

detects the phase difference between PCLK/M and SYNCLK/N and adjusts the phase of BUSCLK such that

the skew between PCLK/M and SYNCLK/N is minimized. This allows data to be transferred across the

SYNCLK/PCLK boundary without incurring additional latency.

User control is provided by multiply and mode selection terminals. The multiply terminals provide selection of

one of four clock frequency multiply ratios, generating BUSCLK frequencies ranging from 267 MHz to 400 MHz

with clock references ranging from 33 MHz to 100 MHz. The CDCR81 meets Rambus Clock Generator,

Revision 1.0 specification up to 300 MHz. The mode select terminals can be used to select a bypass mode

where the frequency multiplied reference clock is directly output to the Rambus channel for systems where

synchronization between the Rambus clock and a system clock is not required. Test modes are provided to

bypass the PLL and output REFCLK on the Rambus channel and to place the outputs in a high-impedance state

for board testing.

Copyright

© 1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Direct Rambus and Rambus are trademarks of Rambus Inc.

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REFCLK

GNDP

GNDI

PCLKM

SYNCLKN

GNDC

STOPB

PWRDNB

S0

S1

GNDO

CLK

NC

CLKB

GNDO

MULT0

MULT1

S2

DBQ PACKAGE

(TOP VIEW)

NC – No internal connection