CDCR81

DIRECT RAMBUS

™ CLOCK GENERATOR

SCAS606B – NOVEMBER 1998 – REVISED NOVEMBER 1999

5

POST OFFICE BOX 655303

recommended operating conditions

MIN

NOM

MAX

UNIT

Supply voltage, VDD

3.135

3.3

3.465

V

High-level input voltage, VIH (CMOS)

0.7

×VDD

V

Low-level input voltage, VIL (CMOS)

0.3

×VDD

V

Initial phase error at phase detector inputs

(required range for phase aligner)

– 0.5

×tc(PD)

0.5

×tc(PD)

REFCLK low-level input voltage, VIL

0.3

×VDDIR

V

REFCLK high-level input voltage, VIH

0.7

×VDDIR

V

Input signal low voltage, VIL (STOPB)

0.3

×VDDIPD

V

Input signal high voltage, VIH (STOPB)

0.7

×VDDIPD

V

Input reference voltage for (REFCLK) (VDDIR)

1.235

3.465

V

Input reference voltage for (PCLKM and SYSCLKN) (VDDIPD)

1.235

3.465

V

High-level output current, IOH

–16

mA

Low-level output current, IOL

16

mA

Operating free-air temperature, TA

0

85

°C

timing requirements

MIN

MAX

UNIT

Input cycle time, tc(in)

10

40

ns

Input cycle-to-cycle jitter

250

ps

Input duty cycle over 10,000 cycles

40%

60%

Input frequency modulation, fmod

30

33

kHz

Modulation index, non-linear maximum 0.5%

0.6%

Phase detector input cycle time (PCLKM and SYNCLKN)

30

100

ns

Input slew rate, SR

1

4

V/ns

Input duty cycle (PCLKM and SYNCLKN)

25%

75%