3

Functional Diagram

CD74HC137, CD74HCT137 TRUTH TABLE

INPUTS

OUTPUTS

LE

X

X

H

X

X

X

HHHHHHHH

X

L

X

X

X

X

HHHHHHHH

L

H

LLLLL

H

H

H

H

H

H

H

LHL

L

LH

HLH

H

H

H

H

H

LHL

L

HLH

HLH

H

H

H

H

L

H

L

L

HHHHH

L

HHHH

LHLHL

LH

H

H

HLH

H

H

LHLHLH

H

H

H

H

HLH

H

LHLH

HLH

H

H

H

H

H

LH

LHLH

H

H

H

H

H

H

H

H

HL

H

H

L

X

X

X

Depends upon the address previously applied while LE was at a logic low.

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

CD74HC237, CD74HCT237 TRUTH TABLE

INPUTS

OUTPUTS

LE

X

X

H

X

X

X

LLLLLLLL

X

L

X

X

X

X

LLLLLLLL

L

H

LLLL

H

L

LLLLLL

LHL

L

LHLHL

L

L

L

L

L

L

H

LL

H

L

LL

H

L

LLLL

L

H

LL

H

H

LLL

H

LLLL

LHLHL

L

L

L

L

LHL

L

L

LHLHLHL

L

L

L

LHL

L

LHLH

HL

L

L

L

L

L

LHL

L

H

L

H

H

H

LLLLLLL

H

H

H

L

X

X

X

Depends upon the address previously applied while LE was at a logic low.

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

15

14

13

12

10

7

9

11

1

3

237

137

6

2

4

5

LE

3-BIT

LATCH

1 OF 8

DECODER

GND = 8

HC/HCT HC/HCT

CD74HC137, CD74HCT137, CD74HC237, CD74HCT237