CD74ACT297

DIGITAL PHASE-LOCKED LOOP

SCHS297A – AUGUST 1998 – REVISED SEPTEMBER 1999

10

POST OFFICE BOX 655303

92CS-43152

φB

φA2

ECPD OUT

tPHL

tPLH

3 V

0 V

VOL

≈VCC

50% VCC

1.5 V

50% VCC

1.5 V

1.5 V

3 V

0 V

Figure 9. Waveforms Showing Phase Input (

φB, φA2) to Output (ECPD OUT) Propagation Delays

92CS-40453

D/U

ENCTR

K CLK

1/fmax

tsu

tw

tsu

tH

tH

NOTE A: Shaded areas indicate when the input is permitted to change for predictable output performance.

3 V

0 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

3 V

0 V

Figure 10. Waveforms Showing Clock (K CLK) Pulse Duration and Maximum Clock Pulse Frequency,

and Inputs (D/U, ENCTR) to Clock (K CLK) Setup and Hold Times.

(unless otherwise noted)

PARAMETER

FROM

TO

TA = 25°C

MIN

MAX

UNIT

PARAMETER

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

MAX

UNIT

f

K CLK

I/D OUT

55

45

MHz

fmax

I/D CLK

I/D OUT

40

35

MHz

tPLH

I/D CLK

I/D OUT

19

24

ns

tPHL

I/D CLK

I/D OUT

19

24

ns

tPHL

φA2

ECPD OUT

24

30

ns

tPLH

φA

XORPD OUT

17

22

ns

tPHL

φA1

XORPD OUT

17

22

ns

tPLH

φB

XORPD OUT

17

22

ns

tPHL

φB

XORPD OUT

17

22

ns

tPLH

φB

ECPD OUT

24

30

ns