CD74ACT297

DIGITAL PHASE-LOCKED LOOP

SCHS297A – AUGUST 1998 – REVISED SEPTEMBER 1999

8

POST OFFICE BOX 655303

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

PARAMETER

TA = 25°C

MIN

MAX

UNIT

PARAMETER

MIN

MAX

MIN

MAX

UNIT

f lk

Clock frequency

K CLK

55

45

MHz

fclock

Clock frequency

I/D CLK

40

35

MHz

t

Pulse duration

K CLK

6

8

ns

tw

Pulse duration

I/D CLK

7

9

ns

t

Setup time before K CLK

↑

D/U

13

17

ns

tsu

Setup time before K CLK

↑

ENCTR

12

16

ns

th

Hold time after K CLK

↑

D/U

3

7

ns

th

Hold time after K CLK

↑

ENCTR

2

6

ns

Carry Pulse

(Internal Signal)

Borrrow Pulse

(Internal Signal)

I/D CLK

I/D OUT

92CS-40449

Figure 4. I/D OUT In Lock Condition

φB

92CS-40450

φA2

ECPD OUT

Figure 5. Edge-Controlled Phase-Comparator Waveforms