M68HC08 datasheet(84/188 Pages) FREESCALE

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Internal Clock Generator Module (ICG)

Data Sheet

MC68HC908RF2 — Rev. 4.0

Internal Clock Generator Module (ICG)

MOTOROLA

Figure 6-9. Code Example for Writing DDIV and DSTG

6.4.8 Trimming Frequency on the Internal Clock Generator

The unadjusted frequency of the low-frequency base clock (IBASE), when the

comparators in the frequency comparator indicate zero error, will vary as much as

±25 percent due to process, temperature, and voltage dependencies. These

dependencies are in the voltage and current references, the offset of the

comparators, and the internal capacitor. The voltage and temperature

dependencies have been designed to be a maximum of approximately

±1 percent

error. The process dependencies account for the rest.

Fortunately, for an individual part, the process dependencies are constant. An

individual part can operate at approximately

±2 percent variance from its

unadjusted operating point over the entire specification range of the application. If

the unadjusted operating point can be changed, the entire variance can be limited

±2 percent.

;DDIV and DSTG modification code example

;Changes DDIV and DSTG according to the initial and

; desired clock period values

;Requires ICGON to be clear (disabled)

;User must previously calculate DVFACT and STFACT by

; the equations listed in the specification

;Modifies X and A registers

start

lda

icgcr

;Verify ICGON clear (this will require

cmp

#13

; CMIE,CMF,CMON,ICGON,ICGS clear and CS,ECGON,ECGS set)

lda

#dvfact ;Add the DDIV factor (calculated before

add

icgdvr

; coding by the DDIV2 equation)

sta

icgdvr

lda

#stfact ;Load the DSTG factor (calculated before coding and

; multiplied by 128 to make it 0-255 for maximum precision

ldx

icgdsr

;Load current stage register contents

mul

;Multiply factor times current value

rola

;Since factor was multiplied by 128,

rolx

; result is x6-x0:a7, so put it all in X

bcc

store

;If result is >255, rolx will set carry

rorx

; so divide result by two and

inc

; add one to DDIV

store

stx

icgdsr

;Store value

lda

icgdvr

;Test to see if DDIV too high or low

cmp

#09

;Valid range 0-9; too low is FF/FE; too high is 0A/0B

bhi

exit

;If DDIV is 0-9, you’re almost done

lda

#09

;Otherwise, maximize period and execute error code

sta

icgdvr

jmp

error

exit

jmp

enable

;Jump to code which turns on desired

;clock, clock monitor, interrupts, etc.

Freescale Semiconductor, Inc.

For More Information On This Product,

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