M68HC08 datasheet(79/188 Pages) FREESCALE

79 / 188 page

Internal Clock Generator Module (ICG)

Usage Notes

MC68HC908RF2 — Rev. 4.0

Data Sheet

MOTOROLA

Internal Clock Generator Module (ICG)

6.4.4.2 Binary Weighted Divider

The binary weighted divider divides the output of the ring oscillator by a power of 2,

specified by the DCO divider control bits (DDIV[3:0]). DDIV maximizes at %1001

(values of %1010 through %1111 are interpreted as %1001), which corresponds

to a divide by 512. When DDIV is %0000, the ring oscillator’s output is divided by 1.

Incrementing DDIV by 1 will double the period; decrementing DDIV will halve the

period. The DLF cannot directly increment or decrement DDIV; DDIV is only

incremented or decremented when an addition or subtraction to DSTG carries or

borrows.

6.4.4.3 Variable-Delay Ring Oscillator

The variable-delay ring oscillator’s period is adjustable from 17 to 31 stage delays,

in increments of two, based on the upper three DCO stage control bits (DSTG[7:5]).

A DSTG[7:5] of %000 corresponds to 17 stage delays; DSTG[7:5] of %111

corresponds to 31 stage delays. Adjusting the DSTG[5] bit has a 6.45 percent to

11.8 percent effect on the output frequency. This also corresponds to the size

correction made when the frequency error is greater than

±15 percent. The value

of the binary weighted divider does not affect the relative change in output clock

period for a given change in DSTG[7:5].

6.4.4.4 Ring Oscillator Fine-Adjust Circuit

The ring oscillator fine-adjust circuit causes the ring oscillator to effectively operate

at non-integer numbers of stage delays by operating at two different points for a

variable number of cycles specified by the lower five DCO stage control bits

(DSTG[4:0]). For example, when DSTG[7:5] is %011, the ring oscillator nominally

operates at 23 stage delays. When DSTG[4:0] is %00000, the ring will always

operate at 23 stage delays. When DSTG[4:0] is %00001, the ring will operate at 25

stage delays for one of 32 cycles and at 23 stage delays for 31 of 32 cycles.

Table 6-3. Quantization Error in ICLK

DDIV[3:0]

ICLK Cycles

Bus Cycles

tICLK Q-ERR

%0000 (min)

1.61%–2.94%

%0000 (min)

≥ 32

≥ 8

0.202%–0.368%

%0001

0.806%–1.47%

%0001

≥ 16

≥ 4

0.202%–0.368%

%0010

0.403%–0.735%

%0010

≥ 8

≥ 2

0.202%–0.368%

%0011

≥ 4

≥ 1

0.202%–0.368%

%0100

≥ 2

≥ 1

0.202%–0.368%

%0101–%1001 (max)

≥ 1

0.202%–0.368%

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

M68HC08 датащи(PDF) 79 Page - Freescale Semiconductor, Inc

M68HC08 датащи(HTML) 79 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL