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LTC4218IGN датащи(PDF) 14 Page - Linear Technology |
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LTC4218IGN датащи(HTML) 14 Page - Linear Technology |
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14 / 16 page ![]() LTC4218 14 4218fb Figure 7. 3.3V, 6A Card Resident Application CT 0.1 μF C1 0.1 μF R5 14.7k R6 10k R2 17.4k ADC R3 3.16k R4 10k 3.3V RMON 20k 4218 F07 R7 10k CL 330 μF SENSE– GATE SENSE+ VDD UV SOURCE FB PG GND IOUT LTC4218GN OV INTVCC TIMER FLT R1 10 Ω RS 2m Ω Q1 Si7104DN 3.3V + RGATE 1k CGATE 0.01 μF VOUT 3.3V 6A APPLICATIONS INFORMATION After the 1.2ms timeout the FLT pin needs to pull down on the UV pin to restart the power-up sequence. Since the default values for overvoltage, undervoltage and powergood thresholds for the 12V fixed version match the requirements, no external components are required for the UV, OV and FB pins. The final schematic results in very few external com- ponents. Resistor R1 (10 Ω) prevents high frequency oscillations in Q1 while RGATE of 1k isolates CGATE during fast turn-off. The pull-up resistor, (R2), connects to the PG pin while the 20k (R3) converts the IMON current to a voltage at a ratio: V µA mV mV A k V A IMON == 667 2 20 0 267 . •• . In addition, there is a 0.1μF bypass (C1) on the INTVCC pin. Layout Considerations To achieve accurate current sensing, a Kelvin connection for the sense resistor is recommended. The PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistors and the power MOSFETs should include good thermal management techniques for optimal device power dissipa- tion. A recommended PCB layout for the sense resistor and power MOSFET is illustrated in Figure 6. In Hot Swap applications where load currents can be 6A, narrow PCB tracks exhibit more resistances than wider tracks and operate at elevated temperatures. The minimum trace width for 1oz copper foil is 0.02” per amp to make sure the trace stays at a reasonable temperature. Using 0.03” per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance of about 0.5m Ω/square. Small resistances add up quickly in high current applications It is also important to put C1, the bypass capacitor for the INTVCC pin, as close as possible between the INTVCC and GND. Place the 10 Ω resistor as close as possible to Q1. This will limit the parasitic trace capacitance that leads to Q1 self-oscillation. Additional Applications The LTC4218 has a wide operating range from 2.9V to 26.5V. The UV, OV and PG thresholds are set with a few resistors. All other functions are independent of supply voltage. The last page includes a 24V application with a UV threshold of 19.8V, an OV threshold of 28.3V and a PG threshold of 20.75V. Figure 7 shows a 3.3V application with a UV threshold of 2.87V, an OV threshold of 3.77V and a PG threshold of 3.05V. 4218 F06 R1 RS C Q1 LTC4218 Figure 6. Recommended Layout |
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