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LTC3726IGN датащи(PDF) 14 Page - Linear Technology |
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LTC3726IGN датащи(HTML) 14 Page - Linear Technology |
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14 / 16 page ![]() 14 LTC3726 3726fb APPLICATIO S I FOR ATIO Figure 4. Connections for PolyPhase Operation NDRV UVLO LTC3705/25 (MASTER) VCC SS/FLT FB/IN+ FS/IN– VIN – VIN + VCC PT+ PT– RUN/SS LTC3726 (MASTER) ITH 3726 F05 VOUT + VBIAS FB/PHASE FS/SYNC • • NDRV SS/FLT LTC3705/25 (SLAVE) VCC UVLO FB/IN+ FS/IN– VCC PT+ PT– RUN/SS LTC3726 (SLAVE) ITH FB/PHASE FS/SYNC • • PolyPhase Applications Figure 4 shows the basic connections for using the LTC3705/LTC3725 and LTC3726 in PolyPhase applica- tions. One of the phases is always identified as the “mas- ter,” while all other phases are “slaves.” For the LTC3705/ LTC3725 (primary side), the master monitors the VIN voltage for undervoltage, performs the open-loop start-up and supplies the initial VCC voltage for the master and all slaves. The LTC3705/LTC3725 slaves simply stand by and wait for PWM signals from their respective pulse trans- formers. Since the SS/FLT pins of each master and slave LTC3705/LTC3725s are interconnected, a FAULT (overcurrent, etc.) on any one of the phases will perform a shutdown/restart on all phases together. The LTC3705/ LTC3725 is put into slave mode by omitting the resistor on FS/IN–. For the LTC3726, the master performs soft-start and voltage-loop regulation by driving all slaves to the same current as the master using the ITH pins. Faults and shutdowns are communicated via the interconnection of the RUN/SS pins. The LTC3726 is put into slave mode by tying the FB pin to VCC. |
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