FD7T Series Multi-Output

CMOS Clock Oscillator

May 2008

Item

Min

Max

Unit

Condition

www.pletronics.com

425-776-1880

10

Output Skew

--

60

pS

OUT1 to OUT2

--

160

pS

OUT3 to OUT7

LVCMOS Output Parameters for V

“L” Version

Output High, V

1.6

--

V

I

1.4

--

V

I

1.1

--

V

I

Output Low, V

--

0.1

V

I

--

0.3

V

I

--

0.6

V

I

Rise & Fall Time

0.7

nS

V

Output Symmetry

45

55

%

at 50% point of V

DDOUT

Peak-to-Peak Jitter

(1)(2)

--

140

pS

1 PLL Switching

--

190

pS

4 PLLs Switching

Cycle-to-Cycle Jitter

(1)(2)

--

120

pS

1 PLL Switching

--

170

pS

4 PLLs Switching

Output Skew

--

60

pS

OUT1 to OUT2

--

160

pS

OUT3 to OUT7

VCXO Function

Vcontrol Input Range Usable

0.5

V

V

The slope is positive

Vcontrol Input Range Allowed

- Direct connect to Vcontrol

- Limit current to

+

0.0

-1.0

V

DD

4.0

V

The slope is positive

Recommend >=1K ohm to Vcontrol

Pull Ability specified in the P.N.

Linearity

-10

+10

%

(1) 10,000 cycles

(2) Jitter depends on the device configuration. Data is taken under the following conditions: 1-PLL; 27MHz Crystal, Out2 and Out3

are 27MHz (measured at Out2). 4-PLL; 27MHz Crystal, Out2 and Out3 are 27MHz (measured at Out2). Out4 is 16.384MHz, Out5 is

74.25MHz, Out6 and Out7 are 48MHz.

Frequency Tolerance:

For the FD7x15T and the FD7x10T devices, Pletronics recommends that the tight

tolerance be required on the PLL outputs only. In this case the reference frequency

output would only achieve ±25ppm tolerance. This will reduce the cost of the device.