FD7T Series Multi-Output

CMOS Clock Oscillator

May 2008

www.pletronics.com

425-776-1880

5

PLL Multipliers

There are up to 4 each independent PLL Multipliers and these can multiply the Reference Oscillator

frequency from 1 (bypass mode) to any value that is <=230MHz (the lowest frequency is the Reference

Oscillator frequency).

Each of the PLL Multipliers can have two setup options, 0 or 1, depending on which option is chosen

and set by the Sx control signals and the user’s definitions are stored in eePROM.

Spread Spectrum

Each PLL has its individual Spread Spectrum (SS) function that can be enabled. This permits the

modulation of the output frequency by a user-set amount. The modulation can be centered on the

output frequency or down side only. Which of the 1 of 8 SS settings is being used is set by the Sx input

and the user definition. The value is a percentage of the output frequency that will be modulated.

SS Option

Down Side Modulation

Centered Modulation

0

No SS

No SS

1

-0.25%

+

_0.25%

2

-0.50%

+

_0.50%

3

-0.75%

+

_0.75%

4

-1.00%

+

_1.00%

5

-1.25%

+

_1.25%

6

-1.50%

+

_1.50%

7

-2.00%

+

_2.00%

Divider Section

The dividers operate on the output of the PLLs. There are two dividers on each PLL that divide by 1

through 127, the value is user defined. There is only 1 setting allowed per divider. These are not set by

the Sx input state.

The dividers add very little jitter to the output signals.

Multiplexers

MUX #1 selects the input to the Divider #1, this can be the reference oscillator signal or the output from

PLL Multiplier #1. MUX #2 through MUX #7 connect various divider outputs to the output buffers.

The device can make only one of the setting of connections shown in the block diagram (only one

pattern stored in eePROM).