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LTC2923IDE датащи(PDF) 12 Page - Linear Technology |
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LTC2923IDE датащи(HTML) 12 Page - Linear Technology |
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12 / 20 page ![]() LTC2923 12 2923fa In this example, all supplies remain low while the ON pin is held below 1.23V. When the ON pin rises above 1.23V, 10µA pulls up CGATE and the gate of the FET at 1000V/s. As the gate of the FET rises, the source follows and pulls up the output to 3.3V at 1000V/s. This output serves as the master signal and is buffered from the RAMP pin to the RAMPBUF pin. As this output and the RAMPBUF pin rise, the current from the TRACK pins is reduced. Conse- quently, the voltage at the slave supply’s outputs in- creases, and the slave supplies track the master supply. When the ON pin is again pulled below 1.23V, 10µA will pull down CGATE and the gate of the FET at 1000V/s. If the loads on the outputs are sufficient, all outputs will track down coincidently at 1000V/s. APPLICATIO S I FOR ATIO Coincident Tracking Example 1ms/DIV 2923 F10b 1V/DIV 1ms/DIV 2923 F10a 1V/DIV Figure 10. Coincident Tracking (from Figure 11) MASTER SLAVE2 SLAVE1 Figure 11. Coincident Tracking Example A typical three supply application is shown in Figure 11. The master signal is a 3.3V module. The slave 1 supply is a 1.8V switching power supply and the slave 2 supply is a 2.5V switching power supply. Both slave supplies track coinci- dently with the 3.3V supply that is controlled with an ex- ternal FET. The ramp rate of the supplies is 1000V/s. The 3-step design procedure detailed previously can be used to determine component values. Only the slave 1 supply is considered here as the procedure is the same for the slave 2 supply. 1. Set the ramp rate of the master signal. From Equation 1: C A Vs nF GATE = µ = 10 1000 10 / 2. Solve for the pair of resistors that provide the desired slave supply behavior, assuming no delay. From Equation 2: Rk Vs Vs k TB = Ω = Ω 16 5 1000 1000 16 5 .• / / . From Equation 3: R V V k V k V k k TA′ = Ω + ΩΩ ≈Ω 08 1 235 16 5 1 235 35 7 08 16 5 13 . . . . . – . . 3. Choose RTA to obtain the desired delay. Since no delay is desired, RTA = RTA′ Q1 CGATE 10nF VCC RONB 138k 3.3V RTB1 16.5k RTB2 887k RFA1 35.7k 1.8V SLAVE1 3.3V MASTER RFB1 16.5k RTA2 412k RTA1 13k RONA 100k ON FB1 GATE LTC2923 GND 2923 F11 RAMP RFA2 412k 2.5V SLAVE2 RFB2 887k RAMPBUF TRACK1 TRACK2 FB2 DC/DC IN 3.3V 3.3V FB = 1.235V OUT DC/DC IN FB = 0.8V OUT 0.1µF 10Ω |
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