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LTC1472CS датащи(PDF) 11 Page - Linear Technology |
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LTC1472CS датащи(HTML) 11 Page - Linear Technology |
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11 / 16 page ![]() 11 LTC1472 1472fa APPLICATIONS INFORMATION Output Capacitors The VCC(OUT) pin is designed to ramp on slowly, typically 400 µs rise time. Therefore, capacitors as large as 150µF can be driven without producing voltage spikes on the 5VIN or 3VIN supply pins (see graphs in Typical Perfor- mance Characteristics). The VCC(OUT) pin should have a 0.1 µF to1µFcapacitorfornoisereductionandsmoothing. The VPPOUT pin should have a 0.01µF to 0.1µF capacitor for noise reduction. The VPPIN capacitors should be at least equal to the VPPOUT capacitors to ensure smooth transitions between output voltages without creating spikes on the system power supply lines. Supply Sequencing Because the 5V supply is the source of power for both the VCC and VPP switch control logic, it is best to sequence the power supplies such that the 5V supply is powered before or simultaneous to the application of 3.3V or 12V power. It is interesting to note however, that all of the switches in the LTC1472 are NMOS transistors which require charge pumps to generate gate voltages higher than the supply rails for full enhancement. Because the gate voltages start a 0V when the supplies are first activated, the switches always start in the off state and do not produce glitches at the output when powered. Some PCMCIA switch matrix products employ PMOS switches for 12V VPP control and great care must be taken to ensure that the 5V control logic is powered before the 12V supply is turned on. If this sequence is not followed, the PMOS VPP switch gate may start at ground potential and the VPP output may be inadvertently forced to 12V. Although, not advisable, it is possible to power the 12V VPPIN supply pin of the LTC1472 prior to application of 5V power. Only about 50 µA flows to the VPPOUT pin under these conditions. If the 5V supply must be turned off, it is important to program all switches to the Hi-Z or 0V state at least 100 µs before the 5V power is removed to ensure that all NMOS switch gates are fully discharged to 0V. Whenever possible however, it is best to leave the 5VIN and VDD pins continuously powered. The LTC1472 quiescent current drops to < 1 µA with all the switches turned off and therefore no 5V power is consumed in the standby mode. |
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