LTC1235

6

1235fa

Logic controls M2. If the status is high, auxiliary power,

is in Battery Saving Mode. If backup battery or auxiliary

pass with a capacitor of 0.1μF or greater. During normal

power switch, M1, which can deliver up to 50mA and has a

the status of the BACKUP pin stored in Memory Logic

controls M2. If the status is high, the Memory Logic turns

M2. If the status is low, the Memory Logic keeps M2 off

bypassed with a 0.1μF capacitor.

GND (Pin 4):

Ground pin.

BATT ON (Pin 5):

Battery on logic output from comparator

base drive for an external PNP transistor to increase the

LOW LINE (Pin 6):

Logic output from comparator C1.

the reset voltage threshold, LOW LINE returns high (see

(see Table 1).

PB RST(Pin 7):

Logic input for direct connection to a push-

button. The push-button reset input requires an active low

signal. Internally, this input signal is debounced and timed

for a minimum of 40ms. When this condition is satisfied,

the reset pulse generator forces RESET to active low. The

RESETsignalwillremainactivelowforaminimumof140ms

PIN FUNCTIONS

from the moment the push-button reset input is released

Backup (Pin 8):

Logic input to control the PMOS switch,

through the reset voltage threshold, the status of the

BACKUP pin (logic low or logic high) is latched in Memory

be pulled high by an internal pullup and the LTC1235 will

PFI (Pin 9):

Power Failure Input. PFI is the noninverting

input to the Power Fail Comparator, C3. The inverting input

is internally connected to a 1.3V reference. The Power

Failure Output remains high when PFI is above 1.3V and

goes low when PFI is below 1.3V. Connect PFI to GND or

PFO (Pin 10): Power Failure Output from C3. PFO remains

high when PFI is above 1.3V and goes low when PFI is

down and PFO is forced low.

WDI (Pin 11):

Watchdog Input, WDI, is a three level

input. Driving WDI either high or low for longer than the

watchdog time-out period, forces both RESET and WDO

low. Floating WDI disables the Watchdog Timer. The timer

resets itself with each transition of the Watchdog Input

(see Figure 11).

CE OUT(Pin 12): Logic output from the Chip Enable gating

the reset voltage threshold CE OUT is forced high (see

Figure 6).

CE IN (Pin 13): Logic input to the Chip Enable gating cir-

cuit. CE IN can be derived from microprocessor’s address

line and/or decoder output. See Applications Information

Section and Figure 6 for additional information.

WDO (Pin 14): Watchdog logic output. When the watch-

dog input remains either high or low for longer than the

watchdog time-out period, WDO goes low. WDO is set