AX2000-1CS896 datasheet(92/226 Pages) ACTEL

номер детали	AX2000-1CS896

подробное описание детали	Axcelerator Family FPGAs

PDF	226 Pages

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производитель	ACTEL [Actel Corporation]

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Axcelerator Family FPGAs

2- 78

v2.7

Table 2-91 • Eight RAM Blocks Cascaded

Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70°C

'–2' Speed

'–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Write Mode

tWDASU

Write Data Setup vs. WCLK

5.78

6.58

7.74

tWDAHD

Write Data Hold vs. WCLK

0.22

0.25

0.3

tWADSU

Write Address Setup vs. WCLK

5.78

6.58

7.74

tWADHD

Write Address Hold vs. WCLK

0.22

0.25

0.3

tWENSU

Write Enable Setup vs. WCLK

5.78

6.58

7.74

tWENHD

Write Enable Hold vs. WCLK

0.22

0.25

0.3

tWCKH

WCLK Minimum High Pulse Width

0.98

1.11

1.31

tWCLK

WCLK Minimum Low Pulse Width

6.68

7.6

8.94

tWCKP

WCLK Minimum Period

13.35

15.21

17.88

Read Mode

tRADSU

Read Address Setup vs. RCLK

6.75

7.69

9.04

tRADHD

Read Address Hold vs. RCLK

0.00

tRENSU

Read Enable Setup vs. RCLK

6.75

7.69

9.04

tRENHD

Read Enable Hold vs. RCLK

0.00

tRCK2RD1

RCLK-To-OUT (Pipelined)

3.574.064.77

tRCK2RD2

RCLK-To-OUT (Non-Pipelined)

5.48

6.24

7.34

tRCLKH

RCLK Minimum High Pulse Width

0.95

1.08

1.27

tRCLKL

RCLK Minimum Low Pulse Width

7.51

8.55

10.05

tRCKP

RCLK Minimum Period

15.02

17.11

20.11

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