LTC1060CSW datasheet(7/20 Pages) LINER

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LTC1060

1060fb

operation of the device. By tying Pin 12 to 1/2 supplies

(which should be the AGND potential), the LTC1060

operates in the 100:1 mode. The 1/2 supply bias of Pin 12

can vary around the 1/2 supply potential without affecting

the 100:1 filter operation. This is shown in Table 1.

When Pin 12 is shorted to the negative supply pin, the filter

operation is stopped and the bandpass and lowpass

outputs act as a S/H circuit holding the last sample. The

hold step is 20mV and the droop rate is 150µV/second!

Table 1

VOLTAGE RANGE OF PIN 12

TOTAL POWER SUPPLY

FOR 100:1 OPERATION

2.5 ± 0.5V

10V

5V ± 1V

15V

7.5V ± 1.5V

S1A, S1B (Pins 5 and 16)

These are voltage signal input pins and, if used, they

should be driven with a source impedance below 5kΩ. The

S1A, S1B pins can be used to alter the CLK to center

frequency ratio (fCLK/f0) of the filter (see Modes 1b, 1c, 2a,

2b) or to feedforward the input signal for allpass filter

configurations (see Modes 4 and 5). When these pins are

not used, they should be tied to the AGND pin.

SA/B (Pin 6)

When SA/B is high, the S2 input of the filter’s voltage

summer (see Block Diagram) is tied to the lowpass output.

This frees the S1 pin to realize various modes of operation

for improved applications flexibility. When the SA/B pin is

connected to the negative supply, the S2 input switches to

ground and internally becomes inactive. This improves

the filter noise performance and typically lowers the value

of the offset VOS2.

AGND (Pln 15)

This should be connected to the system ground for dual

supply operation. When the LTC1060 operates with a

single positive supply, the analog ground pin should be

tied to 1/2 supply and bypassed with a 0.1µF capacitor, as

shown in the application, “Single 5V, Gain of 1000 4th

Order Bandpass Filter.” The positive inputs of all the

Power Supplies

The V +A and V +D (pins 7 and 8) and the V–A and V–D

(Pins 14 and 13) are, respectively, the analog and digital

positive and negative supply pins. For most cases, Pins 7

and 8 should be tied together and bypassed by a 0.1µF disc

ceramic capacitor. The same holds for Pins 13 and 14. If

the LTC1060 operates in a high digital noise environment,

the supply pins can be bypassed separately. Pins 7 and 8

are internally connected through the IC substrate and

should be biased from the same DC source. Pins 13 and

14 should also be biased from the same DC source.

The LTC1060 is designed to operate with ±2.5V supply

(or single 5V) and with ± 5V to ±8V supplies. The mini-

mum supply, where the filter operates reliably, is ± 2.37V.

With low supply operation, the maximum input clock

frequency is about 500kHz. Beyond this, the device exhib-

its excessive Q enhancement and center frequency errors.

Clock Input Pins and Level Shift

The level shift (LSh) Pin 9 is used to accommodate T2L or

CMOS clock levels. With dual supplies equal or higher

to ±4.5V, Pin 9 should be connected to ground (same

potential as the AGND pin). Under these conditions the

clock levels can be T2L or CMOS. With single supply

operation, the negative supply pins and the LSh pin should

be tied to the system ground. The AGND, Pin 15, should

be biased at 1/2 supplies, as shown in the “Single 5V Gain

of 1000 4th Order Bandpass Filter” circuit. Again, under

these conditions, the clock levels can be T2L or CMOS. The

input clock pins (10,11) share the same level shift pin.

The clock logic threshold level over temperature is

typically 1.5V ± 0.1V above the LSh pin potential. The duty

cycle of the input clock should be close to 50%. For clock

frequencies below 1MHz, the (fCLK/f0) ratio is independent

from the clock input levels and from its rise and fall times.

Fast rising clock edges, however, improve the filter DC

offsets. For clock frequencies above 1MHz, T2L level

clocks are recommended.

50/100/Hold (Pin 12)

By tying Pin 12 to (V+A and V +D), the filter operates in the

50:1 mode. With ±5V supplies, Pin 12 can be typically 1V

below the positive supply without affecting the 50:1

PIN DESCRIPTION AND APPLICATIONS INFORMATIO

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