7

LTC1040

1040fa

1A

100mV

APPLICATIO S I FOR ATIO

Offset Voltage Error

The errors due to offset, common mode, power supply

variation, gain and temperature are all included in the

offset voltage specification. This makes it easy to compute

the error when using the LTC1040.

Example: error computation for Figure 4.

Assume: 2.8V

Then total worst-case error is:

Note: If source resistance exceeds 10k, bypass

capacitors should be used and the associated errors must

be included.

It is often desirable to use comparators with resistive

networks such as bridges. Because of the extremely low

power consumption of the LTC1040, the power consumed

by these resistive networks can far exceed that of the

device itself.

At low sample rates the LTC1040 spends most of its time

is on and to a high impedance (open circuit) when the

comparator is off. The ON time is nominally 80

µs.

Voltage versus Load Current curve). There are two ways

excessive errors: (1) ratiometric networks and (2) fast

settling references.

In a ratiometric network, the inputs are all proportional to

It is critical that the inputs to the LTC1040 completely

settle within 4

µs of the start of the comparison cycle and

that they do not change during the 80

µs ON time. When

the network should be minimized to meet the 4

µs settling

to drive networks with source impedances, as seen by the

inputs, of greater than 10k

Ω.

In applications where an absolute reference is required,

reference. The LT1009 2.5V reference, ideal in this

application, settles in approximately 2

µs (see Figure 7).

The current through R1 must be large enough to supply

the LT1009 minimum bias current (

≈1mA) and the load

LTC1040 • AI05

80

µs

COMPARATOR ON TIME

18

917

GND

Q1 P1

=

±6mA

↑↑

Tracking Error

• 100 =

± 0.6%.

6mA

1A

OUTPUT

LTC1040 • AI06

–

–+

–

+

+

1/2

LTC1040

LTC1040 • AI07

–

–

+

+

1/2

LTC1040

R2

R3

LT1009

R1