4-263

TELCOM SEMICONDUCTOR, INC.

7

6

5

4

3

1

2

8

LOGIC-INPUT CMOS

QUAD DRIVERS

TC4467

TC4468

TC4469

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

Input

Logic 1, High Input Voltage

(Note 3)

2.4

—

—

V

Logic 0, Low Input Voltage

(Note 3)

—

—

0.8

V

Input Current

0V

– 10

—

10

µA

Output

High Output Voltage

—

—

V

Low Output Voltage

—

—

0.30

V

Output Resistance

—

20

30

Ω

Peak Output Current

—

1.2

—

A

I

Latch-Up Protection

4.5V

500

—

—

mA

Withstand Reverse Current

Switching Time

Rise Time

Figure 1

—

—

50

nsec

Fall Time

Figure 1

—

—

50

nsec

Delay Time

Figure 1

—

—

100

nsec

Delay Time

Figure 1

—

—

100

nsec

Power Supply

Power Supply Current

—

—

8

mA

Power Supply Voltage

Note 2

4.5

—

18

V

unless otherwise specified.

NOTES: 1. Totem-pole outputs should not be paralleled because the propagation delay differences from one to the other could cause one driver to

drive high a few nanoseconds before another. The resulting current spike, although short, may decrease the life of the device.

dv/dt will cause high-power dissipation in the device.

3. The input threshold has about 50 mV of hysteresis centered at approximately 1.5V. Slow moving inputs will force the device to

dissipate high peak currents as the input transitions through this band. Input rise times should be kept below 5

µs to avoid high internal

peak currents during input transitions. Static input levels should also be maintained above the maximum or below the minimum input

levels specified in the "Electrical Characteristics" to avoid increased power dissipation in the device.

PIN CONFIGURATIONS

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

2A

2B

3A

3B

GND

V

1Y

2Y

3Y

4Y

4B

4A

DD

1

2

3

4

5

6

7

8

16

13

12

11

10

9

1A

1B

2A

2B

3A

3B

GND

GND

V

1Y

2Y

3Y

4Y

4B

4A

DD

15

14

TC4467/8/9

TC4467/8/9

16-Pin SOIC (Wide)

14-Pin Plastic DIP/CerDIP