AT91SAM9261 datasheet(35/43 Pages) ATMEL

35 / 43 page

6062KS–ATARM–15-Jan-09

AT91SAM9261 Preliminary

10.5

Static Memory Controller

• External memory mapping, 256 Mbyte address space per Chip Select Line

• Up to Eight Chip Select Lines

• 8-, 16- or 32-bit Data Bus

• Multiple Access Modes supported

– Byte Write or Byte Select Lines

– Asynchronous read in Page Mode supported (4- up to 32-byte page size)

• Multiple device adaptability

– Compliant with LCD Module

– Control signal programmable setup, pulse and hold time for each Memory Bank

• Multiple Wait State Management

– Programmable Wait State Generation

– External Wait Request

– Programmable Data Float Time

• Slow Clock Mode Supported

10.6

SDRAM Controller

• Supported Devices

– Standard and Low Power SDRAM (Mobile SDRAM)

• Numerous configurations supported

– 2K, 4K, 8K Row Address Memory Parts

– SDRAM with two or four Internal Banks

– SDRAM with 16- or 32-bit Data Path

• Programming Facilities

– Word, half-word, byte access

– Automatic page break when Memory Boundary has been reached

– Multibank Ping-pong Access

– Timing parameters specified by software

– Automatic refresh operation, refresh rate is programmable

• Energy-saving Capabilities

– Self-refresh, power down and deep power down modes supported

• Error detection

– Refresh Error Interrupt

• SDRAM Power-up Initialization by software

• CAS Latency of 1, 2 and 3 supported

• Auto Precharge Command not used

AT91SAM9261 датащи(PDF) 35 Page - ATMEL Corporation