HSYNCCycle

WINW

WINHC

B1

B2

V

WINSH

PCLK

HD

Data

HSYNCCycle

PAXW

PAXHC

B1

B2

V

IIRSH

PCLK

HD

Data

PAXSH

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Advisory 1.1.1 — H3A data may get corrupted

Workaround(s)

To workaround this problem, use any of the four workarounds described below.

1. Constrain the valid AEW/AF data area. The valid data in the internal line buffer will

not become corrupt under certain constraints. In particular, the problem will not occur

when you adhere to the follow constraints (see figures):

•

B1 + V < 4096 and

•

B2 <= 4096 – (B1+V) + B1

Where

•

B1 = Data area from HD rising edge to start of valid AEW/AF data.

•

V = Valid AEW/AF data area. This is the data area for AEW/AF calculations. This

area is specified using registers in the H3A module. Note that the registers are

different for AEW and for AF. For AEW, bits WINSH specify the horizontal start

position of the AEW windows, bits WINW specify the horizontal width of the

windows, and bits WINHC specify the total number of windows. The total number

of pixels in the valid AEW data area is equal to V=WINW*WINHC. For AF, bits

IIRSH specify the horizontal start position of the IIR filter, bits PAXSH specify the

horizontal start position of the AF paxels, bits PAXW specify the horizontal width

of the paxels, and bits PAXHC specify the total number of paxels. The total

number of pixels in the valid AF data area is equal to V=[ (PAXSH - IIRSH) +

PAXW*PAXHC]. See the VPFE PRG for complete bit descriptions.

•

B2 = Data area from end of valid AEW/AF data to next HD rising edge.

2. Use the imager’s movie readout mode.

In the imager’s movie readout mode the problem does not occur, because the

number of horizontal pixels and blacking are is less than 4096 pixels and the H3A

module receives less than 4096 pixel clock cycles between consecutive HD rising

edges.

Note that the number of pixel clock cycles between consecutive HD rising edges that

the H3A module receives is determined by the external or internal timing generator

and also, if used, by the reformatter inside the CCDC. The reformatter is used when

imagers have special readout patterns. For example, if the readout pattern contains

two lines of actual image data per HSYNC, then the reformatter will convert the data

from one to two lines, internally. The number of pixel clock cycles between

consecutive HD rising edges that the H3A modules receives corresponds to the

timing at the output of the reformatter.

SPRZ287A – July 2008 – Revised October 2008

TMS320DM335 Digital Media System-on-Chip (DMSoC)

13

Silicon Revision 1.1

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