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Silicon Revision 1.1 Usage Notes and Known Design Exceptions to Functional

2.1

Usage Notes for Silicon Revision 1.1

2.1.1

Possible Emulator Crash If TCK Frequency Is Greater than MXI Frequency

2.1.2

2.1.3

SD/SDIO card: How to Read M bytes (M=1, 2, 3) from SD or SDIO card

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Silicon Revision 1.1 Usage Notes and Known Design Exceptions to Functional Specifications

Specifications

Usage Notes highlight and describe particular situations where the device's behavior may not match

presumed or documented behavior. This may include behaviors that affect device performance or

functional correctness. These notes will be incorporated into future documentation updates for the device

(such as the device-specific data sheet), and the behaviors they describe will not be altered in future

silicon revisions.

If the frequency of TCK is greater than the frequency of MXI, there is a chance the emulator will crash

when changing the PLL1 clock frequency. This can happen while stepping through code that configures

the PLL1 controller or while using a GEL function that configures the PLL1 controller.

Additionally, the act of applying reset could cause the clock on the TCK pin to stop being generated,

thereby crashing the emulator. This condition happens if the TCK frequency is 2x or greater than the MXI

frequency during reset.

To avoid both of these issues, the MXI clock frequency must be greater than or equal to the TCK clock

frequency.

This does not create any USB functional issues; however, for USB compliance, DM335 designs must

follow the pin connection specified in the USB Reference Resistor Routing figure in the TMS320DM335

Digital Media System-on-Chip (DMSoC) data sheet (literature number SPRS528).

Direction: Read from SD or SDIO

Data size: 32*N+M byte (where M=1, 2, 3 and N=0, 1, 2, 3,...) FIFO size is 32 bytes (ACCWD (FIFOCTL

[4:3] = 0), FIFO trigger level is 256-bits (FIFOLEV (MMCFIFOCTL [2]) =1)

Reading from SD or SDIO when FIFO Trigger Level FIFOLEV is 256 bits causes the

DRRDY(MMCST0[10]) bit not to be set for the last M bytes of the above data size equation and therefore

the DMA read event and CPU interrupt for RRDY(MMCST0[10]) are not getting asserted, but the data in

FIFO is correct.

There are two possible methods to work around this limitation.

1. Include SD status checking and/or SD interrupt enable for TRNDNE (MMCST0 [12]) or DATDNE

(MMCST0 [0])

2. Use 128-bit FIFO trigger level (i.e. FIFOLEV (MMCFIFOCTL [2]) =0), since this is only a problem when

FIFOLEV is 256 bits.

Note:

1. To ensure the start of the MMCSD transfer correctly, the DMATRIG bit (MMCCMD [16]) should always

be set to ‘1’ when writing the command to MMCCMD registers.

2. For SDIO read and write function, the MMCBLEN and MMCNBLK registers have to be set to equal the

total byte count and total block count configured by the SDIO command (CMD52 or CMD53). For

example, to read 3 bytes using CMD53, the software has to set MMCBLEN=3 and MMCNBLK=1.

3. The FIFOFUL and FIFOEMP status bits are set based on access size(ACCWD):

•

If the number of bytes stored in the FIFO is smaller than access size, FIFOEMP is 1. Otherwise,

FIFOEMP is 0.

•

If the size of the remaining empty spaces in FIFO is smaller than access size, FIFOFUL is 1.

Otherwise, FIFOFUL is 0.

SPRZ287A – July 2008 – Revised October 2008

TMS320DM335 Digital Media System-on-Chip (DMSoC)

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Silicon Revision 1.1

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