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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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9202 датащи(PDF) 157 Page - STMicroelectronics |
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9202 датащи(HTML) 157 Page - STMicroelectronics |
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157 / 175 page  157/175 UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV Figure 79. Synchronous Clock Mode Timing – PLD Table 122. CPLD Macrocell Synchronous Clock Mode Timing (5V Devices) Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount. 2. CLKIN (PD1) tCLCL = tCH + tCL. Symbol Parameter Conditions Min Max PT Aloc Turbo Off Slew rate(1) Unit fMAX Maximum Frequency External Feedback 1/(tS+tCO) 40.0 MHz Maximum Frequency Internal Feedback (fCNT) 1/(tS+tCO–10) 66.6 MHz Maximum Frequency Pipelined Data 1/(tCH+tCL) 83.3 MHz tS Input Setup Time 12 + 2 + 10 ns tH Input Hold Time 0 ns tCH Clock High Time Clock Input 6 ns tCL Clock Low Time Clock Input 6 ns tCO Clock to Output Delay Clock Input 13 – 2 ns tARD CPLD Array Delay Any macrocell 11 + 2 ns tMIN Minimum Clock Period(2) tCH+tCL 12 ns tCH tCL tCO tH tS CLKIN INPUT REGISTERED OUTPUT AI02860 |
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